Process optimization for high electron mobility in nMOSFETs with aggressively scaled HfO2/metal stacks

IEEE Electron Device Letters

Volumn 27, Issue 7, 2006, Pages 591-594

  Narayanan, V ^a   Maitra, K ^b,c,d   Linder, B P ^a   Paruchuri, V K ^a   Gusev, E P ^a   Jamison, P ^a   Frank, M M ^a   Steen, M L ^a   La Tulipe, D ^a   Arnold, J ^a   Carruthers, R ^a   Lacey, D L ^a   Cartier, E ^a  

^a IBM RESEARCH   (United States)

^b North Carolina State University   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

^d INTEL CORPORATION   (United States)

Author keywords

Chemical vapor deposition (CVD); Electron mobility; Hafnium oxide (HfO2); High dielectric; Metal gate electrode; Titanium nitride (TiN)

Indexed keywords

CHEMICAL VAPOR DEPOSITION; ELECTRODES; ELECTRON MOBILITY; HAFNIUM COMPOUNDS; HIGH TEMPERATURE EFFECTS; OPTIMIZATION; TITANIUM NITRIDE;

HAFNIUM OXIDE; METAL GATE ELECTRODE; METAL STACKS;

MOSFET DEVICES;

EID: 33745678717     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2006.876312     Document Type: Article

References (20)

1. 2 gate dielectric," in IEDM Tech. Dig., 2002, pp. 433-436.
2. 2 nMOS and pMOSFETs," in IEDM Tech. Dig., 2003, pp. 311-314.
3. V. Narayanan, A. Callegari, F. R. McFeely, K. Nakamura, P. Jamison, S. Zafar, E. Cartier, A. Steegen, V. Ku, P. Nguyen, K. Milkove, C. J. Cabral, M. Gribelyuk, C. Wajda, Y. Kawano, D. Lacey, Y. Li, E. Sikorski, E. Duch, H. Ng, C. Wann, R. Jammy, M. Ieong, and G. Shahidi, "Dual work function metal gate CMOS using CVD metal electrodes," in VLSI Symp. Tech. Dig., 2004, pp. 192-193.
4. 2 gate stacks," in IEDM Tech. Dig., 2004, pp. 825-828.
5. R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros, and M. Metz, "High-κ/metal-gate stack and its MOSFET characteristics," IEEE Electron. Device Lett., vol. 25, no. 6, pp. 408-410, Jun. 2004.
6. P. D. Kirsch, J. H. Sim, S. C. Song, S. Krishnan, J. Peterson, H.-J. Li, M. Quevedo-Lopez, C. D. Young, R. Choi, N. Moumen, P. Majhi, Q. Wang, J. G. Ekerdt, G. Bersuker, and B. H. Lee, "Mobility enhancement of high-κ gate stacks through reduced transient charging," in Proc. 35th Eur. Solid-State Device Res. Conf., Grenoble, France, 2005, pp. 367-370.
7. 2 MISFETs with sub-1 nm EOT," in VLSI Symp. Tech. Dig., 2005, pp. 228-229.
8. 2/TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown (SPER) junctions," in VLSI Symp. Tech. Dig., 2005, pp. 234-235.
9. K. Schroder, Semiconductor Material and Device Characterization, 2nd ed. New York: Wiley, 1998, pp. 544-546.
10. S. Villa, A. L. Lacaita, L. M. Perron, and R. Bez, "A physics based model of the effective mobility in heavily doped NMOSFETs," IEEE Trans. Electron Devices, vol. 45, no. 1, pp. 110-115, Jan. 1998.
11. K. Maitra, "Electron transport in bulk-Si NMOSFETs in presence of high-κ gate insulator - Charge trapping and mobility," Ph.D. dissertation, North Carolina State Univ., Raleigh, 2005.
12. 2 gated silicon field-effect transistors," Appl. Phys. Lett., vol. 85, no. 25, pp. 6230-6232, Dec. 2004.
13. G. Lucovsky and J. C. Philips, "Bond strain and defects in high-κ gate stacks," Microelectron. Reliab., vol. 45, no. 5/6, pp. 770-778, May/Jun. 2005.
14. M. Fischetti, D. Neumayer, and E. Cartier, "Effective electron mobility in Si inversion layers in MOS systems with a high-κ insulator: The role of remote phonon scattering," J. Appl. Phys., vol. 90, no. 9, pp. 4587-4608, Nov. 2001.
15. Z. Ren, M. Fischetti, E. P. Gusev, E. Cartier, and M. Chudzik, "Inversion channel mobility in high-κ high performance MOSFETs," in IEDM Tech. Dig., 2003, pp. 793-796.
16. S. Stemmer, Z. Chen, C. G. Levi, P. S. Lysaght, B. Foran, J. A. Gisby, and J. R. Taylor, "Application of metastable phase diagrams to silicate thin films for alternative gate dielectrics," Jpn. J. Appl. Phys., vol. 42, no. 6A, pt. 1, pp. 3593-3597, Jun. 2003.
17. 2 dielectrics," Appl. Phys. Lett., vol. 85, no. 4, pp. 672-674, Jul. 2004.
18. 2 dielectrics and TiN electrodes," Appl. Phys. Lett., vol. 87, no. 12, pp. 121909-121911, Sep. 2005.
19. S. Saito, D. Hisamoto, S. Kimura, and M. Hiratini, "Unified mobility model for high-κ gate stacks," in IEDM Tech. Dig., 2003, pp. 797-800.
20. J. Li and T.-P. Ma, "Scattering of silicon inversion layer electrons by metal/oxide interface roughness," J. Appl. Phys., vol. 62, no. 10, pp. 4212-4215, Nov. 1987.