Dual work function metal gate CMOS using CVD metal electrodes

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2004, Pages 192-193

  Narayanan, V ^a   Callegari, A ^a   McFeely, F R ^a   Nakamura, K ^a   Jamison, P ^a   Zafar, S ^a   Cartier, E ^a   Steegen, A ^a   Ku, V ^a   Nguyen, P ^a   Milkove, K ^a   Cabral Jr , C ^a   Gribelyuk, M ^a   Wajda, C ^a   Kawano, Y ^a   Lacey, D ^a   Li, Y ^a   Sikorski, E ^a   Duch, E ^a   Ng, H ^a   Wann, C ^a   Jammy, R ^a   Ieong, M ^a   Shahidi, G ^a   more..

^a IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; DEGRADATION; DEPOSITION; DIELECTRIC MATERIALS; DIFFUSION; ELECTRODES; ELECTRON MOBILITY; FABRICATION; HOLE MOBILITY; MOSFET DEVICES; OPTIMIZATION; POLYSILICON;

DAMAGE DEPOSITION PROCESS; METAL GATES; MOBILITY OPTIMIZATION; SPUTTERING DAMAGE;

CMOS INTEGRATED CIRCUITS;

EID: 4544318301     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/vlsit.2004.1345473     Document Type: Conference Paper

References (8)

1. C. Hobbs et al., VLSI Tech Digest. 2003, pg. 9
2. B. Guillaumont et al., IEDM Tech Digest 2002, pg. 355
3. W.Tsai et al., IEDM Tech. Digest 2003, pg. 311
4. S. Datta et al., IEDM Tech. Digest 2003, pg. 653
5. S. Samavedam et al., IEDM Tech. Digest 2002, pg. 433.
6. A. Callegari et al., SSDM 2003, pg. 808
7. A. Callegari et al., VLSI submission 2003(unpublished)
8. S.B, Samavedam et al., IEDM Tech. Digest 2003, pg.307