Potential remedies for the VT/Vfb-shift problem of Hf/polysilicon-based gate stacks: A solution-based survey

Microelectronics Reliability

Volumn 45, Issue 5-6, 2005, Pages 786-789

  Deweerd, W ^a   Kaushik, V ^b   Chen, J ^c   Shimamoto, Y ^d   Schram, T ^a   Ragnarsson, L A ^a   Delabie, A ^a   Pantisano, L ^a   Eyckens, B ^a   Maes, J W ^e   De Gendt, S ^a,f   Heyns, M ^a  

^a IMEC   (Belgium)

^b FREESCALE SEMICONDUCTOR INC   (United States)

^c TEXAS INSTRUMENTS   (United States)

^d IMEC for Renesas ^*

^e ASM BELGIUM   (Belgium)

^f UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CAPPING LAYERS; GATE ELECTRODE DEPOSITION; GATE STACKS; POLY-SI ELECTRODE;

CAPACITORS; CHEMICAL BONDS; CRYSTALLIZATION; ELECTRODEPOSITION; ELECTRODES; FERMI LEVEL; HAFNIUM; INTERFACES (MATERIALS); LITHOGRAPHY; MOSFET DEVICES; POLYSILICON; SEMICONDUCTOR DOPING;

GATES (TRANSISTOR);

EID: 20044387020     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2004.11.048     Document Type: Conference Paper

References (5)

1. L. Colombo proc. of IEDM 2003
2. C. Hobbs VLSI Tech. 2003
3. S. De Gendt proc. of SSICT 2003
4. L.-Å. Ragnarsson proc. of IEDM 2003
5. Q. Lu VLSI Tech. 2002