Ultrathin high-K gate stacks for advanced CMOS devices

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2001, Pages 451-454

  Gusev, E P ^a   Buchanan, D A ^a   Cartier, E ^a   Kumar, A ^a   DiMaria, D ^a   Guha, S ^a   Callegari, A ^a   Zafar, S ^a   Jamison, P C ^b   Neumayer, D A ^a   Copel, M ^a   Gribelyuk, M A ^b   Okorn Schmidt, H ^a   D'Emic, C ^a   Kozlowski, P ^a   Chan, K ^a   Bojarczuk, N ^a   Ragnarsson, L A ^a   Ronsheim, P ^b   Rim, K ^a   Fleming, R J ^b   Mocuta, A ^b   Ajmera, A ^b   more..

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON MOBILITY; ELECTRON TRAPS; GATES (TRANSISTOR); HIGH TEMPERATURE EFFECTS; INTEGRATION; LEAKAGE CURRENTS; METALLORGANIC CHEMICAL VAPOR DEPOSITION; PERMITTIVITY; PHYSICAL VAPOR DEPOSITION; POLYSILICON; THRESHOLD VOLTAGE;

CHARGE TRAPPING; FLATBAND VOLTAGE SHIFTS; GATE LEAKAGE CURRENTS; ULTRATHIN HIGH TEMPERATURE GATE STACKS;

CMOS INTEGRATED CIRCUITS;

EID: 0035716168     PISSN: 01631918     EISSN: None     Source Type: Journal    
DOI: 10.1109/IEDM.2001.979537     Document Type: Article

References (27)