Charge trapping in aggressively scaled metal gate/high-κ stacks

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 729-732

  Gusev, E P ^a   Narayanan, V ^a   Zafar, S ^a   Cabral Jr , C ^a   Cartier, E ^a   Bojarczuk, N ^a   Callegari, A ^a   Carruthers, R ^a   Chudzik, M ^a   D'Emic, C ^a   Duch, E ^a   Jamison, P ^a   Kozlowski, P ^a   LaTulipe, D ^a   Maitra, K ^a   McFeely, F R ^a   Newbury, J ^a   Paruchuri, V ^a   Steen, M ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CMOS INTEGRATED CIRCUITS; ELECTRIC CHARGE; ELECTRIC INSULATORS; ELECTRON MOBILITY; GATES (TRANSISTOR); INTERFACES (MATERIALS); METALLORGANIC CHEMICAL VAPOR DEPOSITION; THRESHOLD VOLTAGE; CHARGE TRAPPING; DIELECTRIC MATERIALS; HAFNIUM COMPOUNDS; PHASE INTERFACES; POLYCRYSTALLINE MATERIALS; REFRACTORY METAL COMPOUNDS;

CHARGE TRAPPING; GATE STACKS; NEGATIVE GATE; VOLTAGE SHIFTS;

ELECTRON TRAPS; SILICIDES;

ANNEALING EFFECTS; CHARGE-TRAPPING; COMPARATIVE ANALYZES; DEPOSITION TECHNIQUE; FORMING GAS; FULLY SILICIDED GATES; GATE ELECTRODE MATERIALS; GATE STACKS; POLY-SI GATES; POST-DEPOSITION;

EID: 20444457876     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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