Physics in fermi level Pinning at the polySi/Hf-based high-k oxide interface

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2004, Pages 108-109

  Shiraishi, K ^a,b   Yamada, K ^b,c   Torii, K ^d   Akasaka, Y ^d   Nakajima, K ^b   Kohno, M ^e   Chikyo, T ^b   Kitajima, H ^d   Arikado, T ^d  

^a UNIVERSITY OF TSUKUBA   (Japan)

^b NATIONAL INSTITUTE FOR MATERIALS SCIENCE   (Japan)

^c WASEDA UNIVERSITY   (Japan)

^d SEMICONDUCTOR LEADING EDGE TECHNOLOGIES INC   (Japan)

^e HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DEPOSITION; DIELECTRIC MATERIALS; ELECTRON TRANSITIONS; FERMI LEVEL; GATES (TRANSISTOR); HAFNIUM COMPOUNDS; METALLIC FILMS; OXIDES; THICKNESS CONTROL;

GATE DIELECTRICS; GATE LEAKAGE; HIGH-K OXIDE INTERFACE; PINNING;

POLYSILICON;

EID: 4544267525     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/vlsit.2004.1345421     Document Type: Conference Paper

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