Nitrogen Profile Control by Plasma Nitridation Technique for Poly-Si Gate HfSiON CMOSFET with Excellent Interface Property and Ultra-low Leakage Current

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2003, Pages 103-106

  Sekine, Katsuyuki ^a   Inumiya, Seiji ^a   Sato, Motoyuki ^a   Kaneko, Akio ^a   Eguchi, Kazuhiro ^a   Tsunashima, Yoshitaka ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CARRIER MOBILITY; CMOS INTEGRATED CIRCUITS; INTERFACES (MATERIALS); LEAKAGE CURRENTS; METALLORGANIC CHEMICAL VAPOR DEPOSITION; NITRIDING; NITROGEN; POLYSILICON; THERMODYNAMIC STABILITY; X RAY PHOTOELECTRON SPECTROSCOPY;

PLASMA NITRIDATION; THERMAL NITRIDATION;

MOSFET DEVICES;

EID: 0842266664     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. M. Koyama, A. Kaneko, T. Ino, M. Koike, Y. Kamata, R. Iijima, Y. Kamimuta, A. Takashima, M. Suzuki, C. Hongo, S. Inumiya, M. Takayanagi and A. Nishiyama, "Effects of nitrogen in HfSiON gate dielectric on the electrical and thermal characteristics", IEDM Tech. Dig. 2002, p.849.
2. A. L. P. Rotondaro, M. R. Visokay, J. J. Chambers, A. Shanware, R. Khamankar, H. Bu, R. T. Laaksonen, L. Tsung, M. Douglas, R. Kuan, M. J. Bevan, T. Grider, J. McPherson, L. Colombo, "Advanced CMOS Transistors with a Novel HfSiON Gate Dielectric", Symp. VLSI Tech. 2002, p. 148.
3. 2 equivalent thickness", IEDM Tech. Dig. 2001, p.137.
4. A. Kaneko, Y. Kamata, M. Ono, M. Koyama, A. Nishiyama, Y. Kamimuta, C. Hongo, A. Takashima, D. Gao, S. Inumiya, K. Eguchi and M. Takayanagi, "Plasma nitridation technique for the formation of thermally stable Hf-silicate gate dielectric with controlled nitrogen profile" Ext. Abst. of SSDM, 2002, p.742
5. S. Inumiya, K. Sekine, S. Niwa, A. Kaneko, M. Sato, T. Watanabe, H. Fukui, Y. Kamata, M. Koyama, A. Nishiyama, M. Takayanagi, K. Eguchi and Y. Tsunashima, "Fabrication of HfSiON gate dielectrics by plasma oxidation and nitridation, optimized for 65nm node low power CMOS applications", Symp. VLSI Tech. 2003, p. 17.
6. T. Watanabe, M. Takayanagi, R. Iijima, K. Ishimaru, H. Ishiuchi and Y. Tsunashima, "Design guideline of HfSiON gate dielectrics for 65 nm CMOS generation", Symp. VLSI Tech. 2003, p.19.