Poly-Si/high-k gate stacks with near-ideal threshold voltage and mobility

2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers

Volumn , Issue , 2005, Pages 97-98

  Frank, M M ^a   Paruchuri, V K ^a   Narayanan, V ^a   Bojarczuk, N ^a   Linder, B ^a   Zafar, S ^a   Cartier, E A ^a   Gusev, E P ^a   Jamison, P C ^a   Lee, K L ^a   Steen, M L ^a   Copel, M ^a   Cohen, S A ^a   Maitra, K ^a   Wang, X ^a   Kozlowski, P M ^a   Newbury, J S ^a   Medeiros, D R ^a   Oldiges, P ^a   Guha, S ^a   Jammy, R ^a   Ieong, M ^a   Shahidi, G ^a   more..

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GATE DIELECTRICS; GATE STACKS; LOW POWER TECHNOLOGIES;

DIELECTRIC MATERIALS; OPTIMIZATION; POLYSILICON; THRESHOLD VOLTAGE;

FIELD EFFECT TRANSISTORS;

EID: 27144558305     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2005.1497093     Document Type: Conference Paper

References (9)

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