Depletion-free poly-Si gate high-k CMOSFETs

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 833-836

  Kim, W S ^a,b   Kamiyama, S ^a   Aoyama, T ^a   Itoh, H ^a   Maeda, T ^a   Kawahara, T ^a   Torii, K ^a   Kitajima, H ^a   Arikado, T ^a  

^a SEMICONDUCTOR LEADING EDGE TECHNOLOGIES INC   (Japan)

^b NONE   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CAPACITORS; CHEMICAL VAPOR DEPOSITION; CMOS INTEGRATED CIRCUITS; DOPING (ADDITIVES); FERMI LEVEL; GATES (TRANSISTOR); NITRIDES; POLYSILICON; THRESHOLD VOLTAGE; ALUMINUM COMPOUNDS; COMPUTER CIRCUITS; GATE DIELECTRICS; HIGH-K DIELECTRIC; POLYCRYSTALLINE MATERIALS; SILICON COMPOUNDS;

FERMI PINNING EFFECT; GATE DEPLETION; GATE DIELECTRIC STACK ENGINEERING; INVERTED GATE IMPLANTATION (IGI);

MOSFET DEVICES; THRESHOLD VOLTAGE;

CMOSFETS; FERMI PINNING EFFECT; GATE DEPLETION; GATE DIELECTRIC STACK ENGINEERING; HIGH- K; INVERTED GATE IMPLANTATIONS; POLY-SI GATES; STACKED GATE DIELECTRICS; SUBTHRESHOLD; SURFACE CHANNEL;

EID: 21644474616     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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