-
1
-
-
0036931225
-
2 gate dielectric MOSFETs using deuterium anneal
-
2 gate dielectric MOSFETs using deuterium anneal," in IEDM Tech. Dig., 2002, pp. 613-616.
-
(2002)
IEDM Tech. Dig.
, pp. 613-616
-
-
Choi, R.1
Onishi, K.2
Kang, C.S.3
Gopalan, S.4
Nieh, R.5
Kim, Y.H.6
Han, J.H.7
Krishnan, S.8
Cho, H.J.9
Shahriar, A.10
Lee, J.C.11
-
2
-
-
0141426796
-
Germanium MOS: An evaluation from carrier quantization and tunneling current
-
T. Low, Y. T. Hou, M. F. Li, C. Zhu, D.-L. Kwong, and A. Chin, "Germanium MOS: An evaluation from carrier quantization and tunneling current," in VLSI Tech. Dig., 2003, pp. 115-118.
-
(2003)
VLSI Tech. Dig.
, pp. 115-118
-
-
Low, T.1
Hou, Y.T.2
Li, M.F.3
Zhu, C.4
Kwong, D.-L.5
Chin, A.6
-
5
-
-
0141761533
-
Strained-Silicon NMOS with nickel-suicide metal gate
-
Q. Xiang, J. S. Goo, J. Pan, B. Yu, S. Ahmed, J. Zhang, and M.-R. Lin, "Strained-Silicon NMOS with nickel-suicide metal gate," in VLSI Tech. Dig., 2003, pp. 103-104.
-
(2003)
VLSI Tech. Dig.
, pp. 103-104
-
-
Xiang, Q.1
Goo, J.S.2
Pan, J.3
Yu, B.4
Ahmed, S.5
Zhang, J.6
Lin, M.-R.7
-
6
-
-
0141426803
-
3 gate dielectrics
-
3 gate dielectrics," in VLSI Tech. Dig., 2003, pp. 119-120.
-
(2003)
VLSI Tech. Dig.
, pp. 119-120
-
-
Huang, C.H.1
Yang, M.Y.2
Chin, A.3
Chen, W.J.4
Zhu, C.X.5
Cho, B.J.6
Li, M.-F.7
Kwong, D.L.8
-
7
-
-
0034798978
-
Effects of high K dielectrics on the workfunctions of metal and silicon gates
-
Y. C. Yeo, P. Ranade, Q. Lu, R. Lin, T. J. King, and C. Hu, "Effects of high K dielectrics on the workfunctions of metal and silicon gates," in VLSI Tech. Dig., 2001, pp. 49-50.
-
(2001)
VLSI Tech. Dig.
, pp. 49-50
-
-
Yeo, Y.C.1
Ranade, P.2
Lu, Q.3
Lin, R.4
King, T.J.5
Hu, C.6
-
8
-
-
0036923598
-
Tunable work function dual metal gate technology for bulk and nonbulk CMOS
-
J. Lee, H. Zhong, Y. S. Suh, G. Heuss, J. Gurganus, B. Chen, and V. Misra, "Tunable work function dual metal gate technology for bulk and nonbulk CMOS," in IEDM Tech. Dig., 2002, pp. 359-362.
-
(2002)
IEDM Tech. Dig.
, pp. 359-362
-
-
Lee, J.1
Zhong, H.2
Suh, Y.S.3
Heuss, G.4
Gurganus, J.5
Chen, B.6
Misra, V.7
-
9
-
-
0035717522
-
2) polysilicon: A novel approach to very low-resistive gate (∼ 2Ω/□) without metal CMP nor etching
-
2) polysilicon: a novel approach to very low-resistive gate (∼ 2Ω/□) without metal CMP nor etching," in IEDM Tech. Dig., 2001, pp. 815-828.
-
(2001)
IEDM Tech. Dig.
, pp. 815-828
-
-
Tavel, B.1
Skotnicki, T.2
Pares, G.3
Carrière, N.4
Rivoire, M.5
Leverd, F.6
Julien, C.7
Torres, J.8
Pantel, R.9
-
10
-
-
0036932380
-
Transistors with dual work function metal gates by single Full Silicidation (FUSI) of polysilicon gates
-
W. P. Maszara, Z. Krivokapic, P. King, J.-S. Goo, and M.-R. Lin, "Transistors with dual work function metal gates by single Full Silicidation (FUSI) of polysilicon gates," in IEDM Tech. Dig., 2002, pp. 367-370.
-
(2002)
IEDM Tech. Dig.
, pp. 367-370
-
-
Maszara, W.P.1
Krivokapic, Z.2
King, P.3
Goo, J.-S.4
Lin, M.-R.5
-
11
-
-
0036923594
-
Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation
-
J. Kedzierski, E. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, R. Carruthers, C. Cabrai, R. Amos, C. Lavoie, R. Roy, J. Newbury, E. Sullivan, J. Benedict, P. Saunders, K. Wong, D. Canaperi, M. Krishnan, K.-L. Lee, B. A. Rainey, D. Fried, P. Cottrell, H.-S. P.H.-S. Philip Wong, M. Ieong, and W. Haensch, "Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation," in IEDM Tech. Dig., 2002, pp. 247-250.
-
(2002)
IEDM Tech. Dig.
, pp. 247-250
-
-
Kedzierski, J.1
Nowak, E.2
Kanarsky, T.3
Zhang, Y.4
Boyd, D.5
Carruthers, R.6
Cabrai, C.7
Amos, R.8
Lavoie, C.9
Roy, R.10
Newbury, J.11
Sullivan, E.12
Benedict, J.13
Saunders, P.14
Canaperi, K.D.15
Krishnan, M.16
Lee, K.-L.17
Rainey, B.A.18
Fried, D.19
Cottrell, P.20
Philip Wong, H.-S.P.H.-S.21
Ieong, M.22
Haensch, W.23
more..
-
12
-
-
0041672411
-
3 MOSFETs
-
May
-
3 MOSFETs," IEEE Electron Device Lett., vol. 24, pp. 348-350, May 2003.
-
(2003)
IEEE Electron Device Lett.
, vol.24
, pp. 348-350
-
-
Lin, C.Y.1
Li, H.Y.2
Chin, A.3
Yeo, Y.C.4
Chunxiang Zhu, C.5
Li, M.F.6
Kwong, D.L.7
-
13
-
-
0002298163
-
The strong degradation on 30 Å oxide integrity contaminated by copper
-
Y. H. Lin, Y. C. Chen, K. T. Chan, F. M. Pan, I. J. Hsieh, and A. Chin, "The strong degradation on 30 Å oxide integrity contaminated by copper," J. Electrochem. Soc., vol. 148, no. 4, pp. F73-F76,2001.
-
(2001)
J. Electrochem. Soc.
, vol.148
, Issue.4
-
-
Lin, Y.H.1
Chen, Y.C.2
Chan, K.T.3
Pan, F.M.4
Hsieh, I.J.5
Chin, A.6
-
14
-
-
0036687166
-
0.7-Si
-
Aug.
-
0.7-Si," IEEE Electron Device Lett., vol. 23, pp. 464-466, Aug. 2002.
-
(2002)
IEEE Electron Device Lett.
, vol.23
, pp. 464-466
-
-
Lin, C.Y.1
Chen, W.J.2
Lai, C.H.3
Chin, A.4
Liu, J.5
-
15
-
-
0347131291
-
Fully suicided NiSi and germanided NiGe dual gates on SiO2 n- and p-MOSFETs
-
Dec.
-
D. S. Yu, C. H. Wu, C. H. Huang, A. Chin, W. J. Chen, C. Zhu, M. F. Li, and D.-L. Kwong, "Fully suicided NiSi and germanided NiGe dual gates on SiO2 n- and p-MOSFETs," IEEE Electron Device Lett., vol. 24, pp. 739-741, Dec. 2003.
-
(2003)
IEEE Electron Device Lett.
, vol.24
, pp. 739-741
-
-
Yu, D.S.1
Wu, C.H.2
Huang, C.H.3
Chin, A.4
Chen, W.J.5
Zhu, C.6
Li, M.F.7
Kwong, D.-L.8
|