Overview and outlook of three-dimensional integrated circuit packaging, three-dimensional Si integration, and three-dimensional integrated circuit integration

Journal of Electronic Packaging

Volumn 136, Issue 4, 2014, Pages

  Lau, John H ^a  

^a ASM Pacific Technology   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS PACKAGING; INTEGRATED CIRCUIT MANUFACTURE; SILICON WAFERS; SUPPLY CHAINS; TIMING CIRCUITS;

3-D INTEGRATION; CIRCUIT INTEGRATION; INTEGRATED-CIRCUIT PACKAGING; MICRO-BUMPS; SI INTEGRATED; SI INTEGRATIONS; SILICON VIA; STATE OF THE ART; THIN CHIPS; THIN WAFERS;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 84993993801     PISSN: 10437398     EISSN: 15289044     Source Type: Journal    
DOI: 10.1115/1.4028629     Document Type: Review

References (150)

1. Lau, J. H., 2013, Through-Silicon Vias for 3D Integration, McGraw-Hill, New York.
2. Lau, J. H., 2011, Reliability of RoHS Compliant 2D & 3D IC Interconnects, McGraw-Hill, New York.
3. Lau, J. H., Lee, C. K., Premachandran, C. S., and Yu, A., 2010, Advanced MEMS Packaging, McGraw-Hill, New York.
4. Moore, G., 1965, "Cramming More Components Onto Integrated Circuits," Electronics, 38(8), pp. 114-117.
5. Lau, J. H., Tzeng, P., Lee, C., Zhan, C., Li, M., Cline, J., Saito, K., Hsin, Y., Chang, P., Chang, Y., Chen, J., Chen, S., Wu, C., Chang, H., Chien, C., Lin, C., Ku, T., Lo, R., and Kao, M., 2014, "Redistribution Layers (RDLs) for 2.5D/3D IC Integration," IMAPS J. Microelectron. Electron. Packag., 11(1), pp. 16-24.
6. Lau, J. H., 2014, "The Future of Interposer for Semiconductor IC Packaging," Chip Scale Rev., 18(1), pp. 32-36.
7. Hsieh, M. C., Wu, S. T., Wu, C. J., and Lau, J. H., 2014, "Energy Release Rate Estimation for Through Silicon Vias in 3-D IC Integration," IEEE Trans. CPMT, 4(1), pp. 57-65.
8. Lau, J. H., 2013, "Supply Chains for High-Volume Manufacturing of 3D IC Integration," Chip Scale Rev., 17(1), pp. 33-39.
9. Khan, N., Li, H., Tan, S., Ho, S., Kripesh, V., Pinjala, D., Lau, J. H., and Chuan, T., 2013, "3-D Packaging With Through-Silicon Via (TSV) for Electrical and Fluidic Interconnections," IEEE Trans. CPMT, 3(2), pp. 221-228.
10. Lau, J. H., and Tang, G. Y., 2012, "Effects of TSVs (Through-Silicon Vias) on Thermal Performances of 3D IC Integration System-In-Package (SiP)," J. Microelectron. Reliab., 52(11), pp. 2660-2669.
11. Lau, J. H., 2012, "Recent Advances and New Trends in Nanotechnology and 3D Integration for Semiconductor Industry," ECS Trans., 44(1), pp. 805-825.
12. Chien, H. C., Lau, J. H., Chao, Y., Tain, R., Dai, M., Wu., S. T., Lo, W., and Kao, M. J., 2012, "Thermal Performance of 3D IC Integration With Through-Silicon Via (TSV)," IMAPS J. Microelectron. Electron. Packag., 9(2), pp. 97-103.
13. Chen, J. C., Lau, J. H., Tzeng, P. J., Chen, S., Wu, C., Chen, C., Yu, H., Hsu, Y., Shen, S., Liao, S., Ho, C., Lin, C., Ku, T. K., and Kao, M. J., 2012, "Effects of Slurry in Cu Chemical Mechanical Polishing (CMP) of TSVs for 3-D IC Integration," IEEE Trans. CPMT, 2(6), pp. 956-963.
14. Lee, C. K., Chang, T. C., Lau, J. H., Huang, Y., Fu, H., Huang, J., Hsiao, Z., Ko, C., Cheng, R., Chang, P., Kao, K., Lu, Y., Lo, R., and Kao, M., 2012, "Wafer Bumping, Assembly, and Reliability of Fine-Pitch Lead-Free Micro Solder Joints for 3-D IC Integration," IEEE Trans. CPMT, 2(8), pp. 1229-1238.
15. Sekhar, V. N., Shen, L., Kumar, A., Chai, T. C., Zhang, X., Premchandran, C. S., Kripesh, V., Yoon, S., and Lau, J. H., 2012, "Study on the Effect of Wafer Back Grinding Process on Nanomechanical Behavior of Multilayered Low-K Stack," IEEE Trans. CPMT, 2(1), pp. 3-12.
16. Zhang, X., Rajoo, R., Selvanayagam, C. S., Kumar, A., Rao, V., Khan, N., Kripesh, V., Lau, J. H., Kwong, D., Sundaram, V., and Tummala, R. R., 2012, "Application of Piezoresistive Stress Sensor in Wafer Bumping and Drop Impact Test of Embedded Ultra-thin Device," IEEE Trans. CPMT, 2(16), pp. 935-943.
17. Wu, C., Chen, S., Tzeng, P., Lau, J. H., Hsu, Y., Chen, J., Hsin, Y., Chen, C., Shen, S., Lin, C., Ku, T., and Kao, M., 2012, "Oxide Liner, Barrier and Seed Layers, and Cu-Plating of Blind Through Silicon Vias (TSVs) on 300 mm Wafers for 3D IC Integration," IMAPS J. Microelectron. Electron. Packag., 9(1), pp. 31-36.
18. Lau, J. H., Zhang, M. S., and Lee, S. W. R., 2011, "Embedded 3D Hybrid IC Integration System-in-Package (SiP) for Opto-Electronic Interconnects in Organic Substrates," ASME J. Electron. Packag., 133(3), pp. 1-7.
19. Chai, T. C., Zhang, X., Lau, J. H., Selvanayagam, C. S., Pinjala, D., Hoe, Y., Ong, Y., Rao, V., Wai, E., Li, H., Liao, E., Ranganathan, N., Kripesh, V., Liu, S., Sun, J., Ravi, M., Vath, C. III, and Tsutsumi, Y., 2011, "Development of Large Die Fine-Pitch Cu/Low-k FCBGA Package With Through Silicon Via (TSV) Interposer," IEEE Trans. CPMT, 1(5), pp. 660-672.
20. Lau, J. H., 2011, "TSV Interposers: The Most Cost-Effective Integrator for 3D IC Integration," Chip Scale Rev., 15(5), pp. 23-27.
21. Kumar, A., Zhang, X., Zhang, Q., Jong, M., Huang, G., Lee, V., Kripesh, V., Lee, C., Lau, J. H., Kwong, D., Sundaram, V., Tummula, R. R., and Meyer-Berg, G., 2011, "Residual Stress Analysis in Thin Device Wafer Using Piezo-resistive Stress Sensor," IEEE Trans. CPMT, 1(6), pp. 841-851.
22. Yu, A., Lau, J. H., Ho, S., Kumar, A., Hnin, W., Lee, W., Jong, M., Sekhar, V., Kripesh, V., Pinjala, D., Chen, S., Chan, C., Chao, C., Chiu, C., Huang, C., and Chen, C., 2011, "Fabrication of High Aspect Ratio TSV and Assembly With Fine-Pitch Low-Cost Solder Microbump for Si Interposer Technology With High-Density Interconnects," IEEE Trans. CPMT, 1(9), pp. 1336-1344.
23. Ong, Y. Y., Ho, S., Sekhar, V., Ong, X., Ong, J., Zhang, X., Kripesh, V., Yoon, S., Lau, J. H., Lim, Y., Yeo, D., Chan, K., Zhang, Y., Tan, J., and Sohn, D., 2011, "Underfill Selection, Characterization, and Reliability Study for Fine-Pitch, Large Die Cu/Low-K Flip Chip Package," IEEE Trans. CPMT, 1(3), pp. 279-290.
24. Lau, J. H., 2011, "Overview and Outlook of TSV and 3D Integrations," J. Microelectron. Int., 28(2), pp. 8-22.
25. Lau, J. H., Zhan, C.-J., Tzeng, P.-J., Lee, C.-K., Dai, M.-J., Chien, H.-C., Chao, Y.-L., Li, W., Wu, S.-T., Hung, J.-F., Tain, R.-M., Lin, C.-H., Hsin, Y.-C., Chen, C.-C., Chen, S.-C., Wu, C.-Y., Chen, J.-C., Chien, C.-H., Chiang, C.-W., Chang, H., Tsai, W.-L., Cheng, R.-S., Huang, S.-Y., Lin, Y.-M., Chang, T.-C., Ko, C.-D., Chen, T.-H., Sheu, S.-S., Wu, S.-H., Chen, Y.-H., Lo, W.-C., Ku, T.-K., Kao, M.-J., and Hu, D.-Q., 2011, "Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300mm Multi-Project Wafer (MPW)," IMAPS J. Microelectron. Electron. Packag., 8(4), pp. 171-178.
26. Sheu, S., Lin, Z., Hung, J., Lau, J. H., Chen, P., Wu, S., Su, K., Lin, C., Lai, S., Ku, T., Lo, W., and Kao, M., 2011, "An Electrical Testing Method for Blind Through Silicon Vias (TSVs) for 3D IC Integration," IMAPS J. Microelectron. Electron. Packag., 8(4), pp. 140-145.
27. Lau, J. H., 2010, "Critical Issues of 3D IC Integrations," IMAPS J. Microelectron. Electron. Packag., 7(1), pp. 35-43.
28. Lau, J. H., Chan, Y. S., and Lee, R. S. W., 2010, "3D IC Integration With TSV Interposers for High-Performance Applications," Chip Scale Rev., 14(5), pp. 26-29.
29. Lau, J. H., 2010, "Design and Process of 3D MEMS Packaging," IMAPS J. Microelectron. Electron. Packag., 7(1), pp. 10-15.
30. Lau, J. H., Lee, R., Yuen, M., and Chan, P., 2010, "3D LED and IC Wafer Level Packaging," J. Microelectron. Int., 27(2), pp. 98-105.
31. Lau, J. H., 2010, "State-of-the-Art and Trends in 3D Integration," Chip Scale Rev., 14(2), pp. 22-28.
32. Tang, G. Y., Tan, S., Khan, N., Pinjala, D., Lau, J. H., Yu, A., Kripesh, V., and Toh, K., 2010, "Integrated Liquid Cooling Systems for 3-D Stacked TSV Modules," IEEE Trans. CPMT, 33(1), pp. 184-195.
33. Khan, N., Rao, V., Lim, S., We, H., Lee, V., Zhang, X., Liao, E., Nagarajan, R., Chai, T. C., Kripesh, V., and Lau, J. H., 2010, "Development of 3-D Silicon Module With TSV for System in Packaging," IEEE Trans. CPMT, 33(1), pp. 3-9.
34. Lau, J. H., and Tang, G., 2009, "Thermal Management of 3D IC Integration With TSV (Through Silicon Via)," IEEE 59th Electronic Components and Technology Conference (ECTC 2009), San Diego, CA, May 26-29, pp. 635-640.
35. Yu, A., Khan, N., Archit, G., Pinjala, D., Toh, K., Kripesh, V., Yoon, S., and Lau, J. H., 2009, "Fabrication of Silicon Carriers With TSV Electrical Interconnections and Embedded Thermal Solutions for High Power 3-D Packages," IEEE Trans. CPMT, 32(3), pp. 566-571.
36. Selvanayagam, C., Lau, J. H., Zhang, X., Seah, S., Vaidyanathan, K., and Chai, T. C., 2008, "Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps," IEEE 58th Electronic Components and Technology Conference (ECTC 2008), Lake Buena Vista, FL, May 27-30, pp. 1073-1081.
37. Zhang, X., Kumar, A., Zhang, Q. X., Ong, Y. Y., Ho, S. W., Khong, C. H., Kripesh, V., Lau, J. H., Kwong, D.-L., Sundaram, V., Tummula, R. R., and Meyer-Berg, G., 2009, "Application of Piezoresistive Stress Sensors in Ultra Thin Device Handling and Characterization," J. Sens. Actuators, A, 156(1), pp. 2-7.
38. Lau, J. H., Lee, C.-K., Zhan, C.-J., Wu, S.-T., Chao, Y.-L., Dai, M.-J., Tain, R.-M., Chien, H.-C., Hung, J.-F., Chien, C.-H., Cheng, R.-S., Huang, Y.-W., Cheng, Y.-M., Liao, L.-L., Lo, W.-C., and Kao, M.-J., 2014, "Through-Silicon Hole Interposers for 3-D IC Integration," IEEE Trans. Components, Packaging and Manufacturing Technology, 4(9), pp. 1407-1419.
39. Lau, J. H., Lee, R. S. W., Yuen, M., Wu, J., Lo, C., Fan, H., and Chen, H., 2013, "Apparatus Having Thermal-Enhanced and Cost-Effective 3D IC Integration Structure With Through Silicon Via Interposer," U.S. Patent No. 8,604,603.
40. Tummula, R., and Swaminathan, M., 2008, System-On-Package: Miniaturization of the Entire System, McGraw-Hill, New York.
41. Xie, J., Shi, H., Li, Y., Li, Z., Rahman, A., Chandrasekar, K., Ratakonda, D., Deo, M., Chanda, K., Hool, V., Lee, M., Vodrahalli, N., Ibbotson, D., and Verma, T., 2012, "Enabling the 2.5D Integration," Proceedings of IMAPS International Symposium on Microelectronics, San Diego, CA, Sept. 9-13, pp. 254-267.
42. Li, Z., Shi, H., Xie, J., and Rahman, A., 2012, "Development of an Optimized Power Delivery System for 3D IC Integration With TSV Silicon Interposer," IEEE 62nd Electronic Components and Technology Conference (ECTC), San Diego, CA, May 29-June 1, pp. 678-682.
43. Kwon, W., Kim, M., Chang, J., Ramalingam, S., Madden, L., Tsai, G., Tseng, S., Lai, J., Lu, T., and Chin, S., 2013, "Enabling a Manufacturable 3D Technologies and Ecosystem Using 28nm FPGA With Stack Silicon Interconnect Technology," IMAPS 46th International Symposium on Microelectronics, (IMAPS 2013), Orlando, FL, Sept. 30-Oct. 3, pp. 217-222.
44. Juergen, M., Zoschke, W. K., Klumpp, A., Wieland, R., Klein, M., Nebrich, L., Heinig, A., Limansyah, I., Weber, W., Ehrmann, O., and Reichl, H., 2009, "3D Integration of Image Sensor SiP Using TSV Silicon Interposer," IEEE 11th Electronics Packaging Technology Conference (EPTC '09), Singapore, Dec. 9-11, pp. 795-800.
45. Hsin, Y. C., Chen, C., Lau, J. H., Tzeng, P., Shen, S., Hsu, Y., Chen, S., Wn, C., Chen, J., Ku, T., and Kao, M., 2011, "Effects of Etch Rate on Scallop of Through-Silicon Vias (TSVs) in 200mm and 300mm Wafers," IEEE 61st Electronic Components and Technology Conference (ECTC), Orlando, FL, May 31-June 3, pp. 1130-1135.
46. Garrou, P., Bower, C., and Ramm, P., 2009, 3D Integration: Technology and Applications, Wiley, New York.
47. Ramm, P., Wolf, M., Klumpp, A., Wieland, R., Wunderle, B., Michel, B., and Reichl, H., 2008, "Through Silicon Via Technology - Processes and Reliability for Wafer-Level 3D System Integration," IEEE 58th Electronic Components and Technology Conference (ECTC 2008), Orlando, FL, May 27-30, pp. 847-852.
48. Andry, P. S., Tsang, C. K., Webb, B. C., Sprogis, E. J., Wright, S. L., Bang, B., and Manzer, D. G., 2008, "Fabrication and Characterization of Robust Through-Silicon Vias for Silicon-Carrier Applications," IBM J. Res. Dev., 52(6), pp. 571-581.
49. Knickerbocker, J. U., Andry, P. S., Dang, B., Horton, R. R., Patel, C. S., Polastre, R. J., Sakuma, K., Sprogis, E. S., Tsang, C. K., Webb, B. C., and Wright, S. L., 2008, "3-D Silicon Integration," IEEE 58th Electronic Components and Technology Conference (ECTC 2008), Lake Buena Vista, FL, May 27-30, pp. 538-543.
50. Shorey, A., Pollard, S., Streltsov, A., Piech, G., and Wagner, R., 2012, "Development of Substrates for Through Glass Vias (TGV) For 3DS-IC Integration," IEEE 62nd Electronic Components and Technology Conference (ECTC), San Diego, CA, May 29-June 1, pp. 289-291.
51. Sundaram, V., Chen, Q., Kumar, G., Liu, F., Tummala, R., and Suzuki, Y., 2012, "Low-Cost and Low-Loss 3D Silicon Interposer for High Bandwidth Logic-to-Memory Interconnections Without TSV in the Logic IC," IEEE 62nd Electronic Components and Technology Conference (ECTC), San Diego, CA, May 29-June 1, pp. 292-297.
52. Lee, H. S., Choi, Y-S., Song, E., Choi, K., Cho, T., and Kang, S., 2007, "Power Delivery Network Design for 3D SIP Integrated Over Silicon Interposer Platform," IEEE 57th Electronic Components and Technology Conference (ECTC '07), Reno, NV, May 29-June 1, pp. 1193-1198.
53. Messemaeker, J., Pedreira, O., Vandevelde, B., Philipsen, H., Wolf, I., Beyne, E., and Croes, K., 2013, "Impact of Post-Plating Anneal and Through-Silicon Via Dimensions on Cu Pumping," IEEE 63rd Electronic Components and Technology Conference (ECTC '13), Las Vegas, NV, May 28-31, pp. 586-591.
54. Morikawa, Y., Murayama, T., Nakamuta, Y., Sakuishi, T., Suzuki, A., and Suu, K., 2013, "Total Cost Effective Scallop Free Si Etching for 2.5D & 3D TSV Fabrication Technologies in 300 mm Wafer," IEEE 63rd Electronic Components and Technology Conference (ECTC), Las Vegas, NV, May 28-31, pp. 605-607.
55. Shi, X., Sun, P., Tsui, Y., Law, P., Yau, S., Leung, C., Liu, Y., Chung, C., Ma, S., Miao, M., and Jin, Y., 2010, "Development of CMOS-Process-Compatible Interconnect Technology for 3D-Stacking of NAND Flash Memory Chips," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 74-78.
56. Kikuchi, K., Ueda, C., Takemura, K., Shimada, O., Gomyo, T., Takeuchi, Y., Ookubo, T., Baba, K., Aoyagi, M., Sudo, T., and Otsuka, K., 2010, "Low-Impedance Evaluation of Power Distribution Network for Decoupling Capacitor Embedded Interposers of 3-D Integrated LSI System," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 1455-1460.
57. Sridharan, V., Min, S., Sundaram, V., Sukumaran, V., Hwang, S., Chan, H., Liu, F., Nopper, C., and Tummala, R., 2010, "Design and Fabrication of Bandpass Filters in Glass Interposer With Through-Package-Vias (TPV)," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 530-535.
58. Sukumaran, V., Chen, Q., Liu, F., Kumbhat, N., Bandyopadhyay, T., Chan, H., Min, S., Nopper, C., Sundaram, V., and Tummala, R., 2010, "Through-Package-Via Formation and Metallization of Glass Interposers," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 557-563.
59. Sakuma, K., Sueoka, K., Kohara, S., Matsumoto, K., Noma, H., Aoki, T., Oyama, Y., Nishiwaki, H., Andry, P. S., Tsang, C. K., Knickerbocker, J., and Orii, Y., 2010, "IMC Bonding for 3D Interconnection," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 864-871.
60. Doany, F., Lee, B., Schow, C., Tsang, C., Baks, C., Kwark, Y., John, R., Knickerbocker, J., and Kash, J., 2010, "Terabit/s-Class 24-Channel Bidirectional Optical Transceiver Module Based on TSV Si Carrier for Board-Level Interconnects," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 58-65.
61. Khan, N., Wee, D., Chiew, O., Sharmani, C., Lim, L., Li, H., and Vasarala, S., 2010, "Three Chips Stacking With Low Volume Solder Using Single Re-Flow Process," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 884-888.
62. Trigg, A., Yu, L., Zhang, X., Chong, C., Kuo, C., Khan, N., and Yu, D., 2010, "Design and Fabrication of a Reliability Test Chip for 3D-TSV," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 79-83.
63. Agarwal, R., Zhang, W., Limaye, P., Labie, R., Dimcic, B., Phommahaxay, A., and Soussan, P., 2010, "Cu/Sn Microbumps Interconnect for 3D TSV Chip Stacking," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 858-863.
64. Töpper, M., Ndip, I., Erxleben, R., Brusberg, L., Nissen, N., Schröder, H., Yamamoto, H., Todt, G., and Reichl, H., 2010, "3-D Thin Film Interposer Based on TGV (Through Glass Vias): An Alternative to Si-Interposer," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 66-73.
65. Liu, H., Wang, K., Aasmundtveit, K., and Hoivik, N., 2010, "Intermetallic Cu3Sn as Oxidation Barrier for Fluxless Cu-Sn Bonding," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 853-857.
66. Kang, I., Jung, G., Jeon, B., Yoo, J., and Jeong, S., 2010, "Wafer Level Embedded System in Package (WL-eSiP) for Mobile Applications," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 309-315.
67. Dorsey, P., 2010, "Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency," Xilinx Inc., San Jose, CA, White Paper Virtex-7 FPGAs, WP380 (v1).
68. Lau, J. H., Lee, C., Zhan, C., Wu, S., Chao, Y., Dai, M., Tain, R., Chien, H., Chien, C., Cheng, R., Huang, Y., Lee, Y., Hsiao, Z., Tsai, W., Chang, P., Fu, H., Cheng, Y., Liao, L., Lo, W., and Kao, M., 2014, "Low-Cost TSH (Through-Silicon Hole) Interposers for 3D IC Integration," IEEE 64th Electronic Components and Technology Conference (ECTC), Orlando, FL, May 27-30, pp. 290-296.
69. Akasaka, Y., 1986, "Three-Dimensional IC Trends," Proc. IEEE, 74(12), pp. 1703-1714.
70. Akasaka, Y., and Nishimura, T., 1986, "Concept and Basic Technologies for 3-D IC Structure," IEEE International Electron Devices Meetings, Los Angeles, CA, Dec. 7-10, pp. 488-491.
71. Dang, B., Andry, P., Tsang, C., Maria, J., Polastre, R., Trzcinski, R., Prabhakar, A., and Knickerbocker, J., 2010, "CMOS Compatible Thin Wafer Processing Using Temporary Mechanical Wafer, Adhesive and Laser Release of Thin Chips/Wafers for 3D Integration," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 1393-1398.
72. Bieck, F., Spiller, S., Molina, F., Töpper, M., Lopper, C., Kuna, I., Seng, T., and Tabuchi, T., 2010, "Carrierless Design for Handling and Processing of Ultrathin Wafers," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 316-322.
73. Itabashi, T., and Zussman, M., 2010, "High Temperature Resistant Bonding Solutions Enabling Thin Wafer Processing (Characterization of Polyimide Base Temporary Bonding Adhesive for Thinned Wafer Handling)," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 1877-1880.
74. Zoschke, K., Wegner, M., Wilke, M., Jürgensen, N., Lopper, C., Kuna, I., Glaw, V., Röder1, J., Wünsch, O., Wolf, M. J., Ehrmann, O., and Reichl, H., 2010, "Evaluation of Thin Wafer Processing Using a Temporary Wafer Handling System as Key Technology for 3D System Integration," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 1385-1392.
75. Charbonnier, J., Hida, R., Henry, D., Cheramy, S., Chausse., P., Neyret, M., Hajji, O., Garnier, G., Brunet-Manquat, C., Haumesser, P., Vandroux, L., Anciant, R., Sillon, N., Farcy, A., Rousseau, M., Cuzzocrea, J., Druais, G., and Saugier, E., 2010, "Development and Characterisation of a 3D Technology Including TSV and Cu Pillars for High Frequency Applications," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 1077-1082.
76. Sun, Y., Li, X., Gandhi, J., Luo, S., and Jiang, T., 2010, "Adhesion Improvement for Polymer Dielectric to Electrolytic-Plated Copper," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 1106-1111.
77. Kawano, M., Takahashi, N., Komuro, M., and Matsui, S., 2010, "Low-Cost TSV Process Using Electroless Ni Plating for 3D Stacked DRAM," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 1094-1099.
78. Malta, D., Gregory, C., Temple, D., Knutson, T., Wang, C., Richardson, T., Zhang, Y., and Rhoades, R., 2010, "Integrated Process for Defect-Free Copper Plating and Chemical-Mechanical Polishing of Through-Silicon Vias for 3D Interconnects," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 1769-1775.
79. Campbell, D. V., 2010, "Yield Modeling of 3D Integrated Wafer Scale Assemblies," IEEE Proceedings of ECTC, 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 1935-1938.
80. Archard, D., Giles, K., Price, A., Burgess, S., and Buchanan, K., 2010, "Low Temperature PECVD of Dielectric Films for TSV Applications," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 764-768.
81. Shigetou, A., and Suga, T., 2010, "Modified Diffusion Bonding for Both Cu and SiO2 at 150°C in Ambient Air," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 872-877.
82. Amagai, M., and Suzuki, Y., 2010, "TSV Stress Testing and Modeling," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 1273-1280.
83. Lu, K., Ryu, S., Zhao, Q., Zhang, X., Im, J., Huang, R., and Ho., P., 2010, "Thermal Stress Induced Delamination of Through Silicon Vias in 3-D Interconnects," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 40-45.
84. Miyazaki, C., Shimamoto, H., Uematsu, T., Abe, Y., Kitaichi, K., Morifuji, T., and Yasunaga, S., 2010, "Development of High Accuracy Wafer Thinning and Pickup Technology for Thin Wafer (Die)," IEEE CPMT Symposium, Tokyo, Japan, Aug. 24-26, pp. 139-142.
85. Cho, J., Yoon, K., Pak, J., Kim, J., Lee, J., Lee, H., Park, K., and Kim, J., 2010, "Guard Ring Effect for Through Silicon Via (TSV) Noise Coupling Reduction," IEEE CPMT Symposium, Tokyo, Japan, Aug. 24-26, pp. 151-154.
86. Nonake, T., Fujimaru, K., Shimada, A., Asahi, N., Tatsuta, Y., Niwa, H., and Tachibana, Y., 2010, "Wafer and/or Chip Bonding Adhesives for 3D Package," IEEE CPMT Symposium, Tokyo, Japan, Aug. 24-26, pp. 169-172.
87. Gupta, A., Kannan, S., Kim, B., Mohammed, F., and Ahn, B., 2010, "Development of Novel Carbon Nanotube TSV Technology," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 1699-1702.
88. Kannan, S., Gupta, A., Kim, B., Mohammed, F., and Ahn, B., 2010, "Analysis of Carbon Nanotube Based Through Silicon Vias," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 51-57.
89. Lau, J. H., 2010, "TSV Manufacturing Yield and Hidden Costs for 3D IC Integration," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 1031-1041.
90. Chen, K., Lee, S., Andry, P., Tsang, C., Topop, A., Lin, Y., Lu, Y. J., Young, A., Ieong, M., and Haensch, W., 2006, "Structure, Design and Process Control for Cu Bonded Interconnects in 3D Integrated Circuits," IEEE International Electron Devices Meeting (IEDM 2006), San Francisco, CA, Dec. 11-13, pp. 367-370.
91. Liu, F., Yu, R., Young, A., Doyle, J., Wang, X., Shi, L., Chen, K., Li, X., Dipaola, D., Brown, D., Ryan, C., Hagan, J., Wong, K., Lu, M., Gu, X., Klymko, N., Perfecto, E., Merryman, A., Kelly, K., Purushothaman, S., Koester, S., Wisnieff, R., and Haensch, W., 2008, "A 300-mm Wafer-Level Three-Dimensional Integration Scheme Using Tungsten Through-Silicon Via and Hybrid Cu-Adhesive Bonding," IEEE International Electron Devices Meeting, San Francisco, CA, Dec. 15-17.
92. Yu, R., Liu, F., Polastre, R., Chen, K., Liu, X., Shi, L., Perfecto, E., Klymko, N., Chace, M., Shaw, T., Dimilia, D., Kinser, E., Young, A., Purushothaman, S., Koester, S., and Haensch, W., 2009, "Reliability of a 300-mm-Compatible 3DI Technology Based on Hybrid Cu-Adhesive Wafer Bonding," Symposium on VLSI Technology, Honolulu, HI, June 16-18, pp. 170-171.
93. Shigetou, A., Itoh, T., Sawada, K., and Suga, T., 2008, "Bumpless Interconnect of 6-μm Pitch Cu Electrodes at Room Temperature," IEEE 58th Electronic Components and Technology Conference (ECTC 2008), Lake Buena Vista, FL, May 27-30, pp. 1405-1409.
94. Tsukamoto, K., Higurashi, E., and Suga, T., 2010, "Evaluation of Surface Microroughness for Surface Activated Bonding," Proceedings of IEEE CPMT Symposium Japan, Tokyo, Japan, Aug. 24-26, pp. 147-150.
95. Kondou, R., Wang, C., and Suga, T., 2010, "Room-Temperature Si-Si and Si- SiN Wafer Bonding," IEEE CPMT Symposium, Tokyo, Japan, Aug. 24-26, pp. 161-164.
96. Shigetou, A., Itoh, T., Matsuo, M., Hayasaka, N., Okumura, K., and Suga, T., 2006, "Bumpless Interconnect Through Ultrafine Cu Electrodes by Means of Surface-Activated Bonding (SAB) Method," IEEE Trans. Adv. Packag., 29(2), pp. 218-226.
97. Wang, C., and Suga, T., 2009, "A Novel Moire Fringe Assisted Method for Nanoprecision Alignment in Wafer Bonding," IEEE 59th Electronic Components and Technology Conference (ECTC 2009), San Diego, CA, May 25-29, pp. 872-878.
98. Wang, C., and Suga, T., 2009, "Moire Method for Nanoprecision Wafer-to-Wafer Alignment: Theory, Simulation and Application," IEEE International Conference on Electronic Packaging Technology and High-Density Packaging (ICEPT-HDP '09), Beijing, China, Aug. 10-13, pp. 219-224.
99. Higurashi, E., Chino, D., Suga, T., and Sawada, R., 2009, "Au-Au Surface-Activated Bonding and Its Application to Optical Microsensors With 3-D Structure," IEEE J. Sel. Topic Quantum Electron., 15(5), pp. 1500-1505.
100. Burns, J., Aull, B., Keast, C., Chen, C., Chen, C., Keast, C., Knecht, J., Suntharalingam, V., Warner, K., Wyatt, P., and Yost, D., 2006, "A Wafer-Scale 3-D Circuit Integration Technology," IEEE Trans. Electron Devices, 53(10), pp. 2507-2516.
101. Chen, C., Warner, K., Yost, D., Knecht, J., Suntharalingam, V., Chen, C., Burns, J., and Keast, C., 2007, "Scaling Three-Dimensional SOI Integrated-Circuit Technology," IEEE International SOI Conference, Indian Wells, CA, Oct. 1-4, pp. 87-88.
102. Chen, C., Chen, C., Yost, D., Knecht, J., Wyatt, P., Burns, J., Warner, K., Gouker, P., Healey, P., Wheeler, B., and Keast, C., 2008, "Three-Dimensional Integration of Silicon-on-Insulator RF Amplifier," Electron. Lett., 44(12), pp. 746-747.
103. Chen, C., Chen, C., Yost, D., Knecht, J., Wyatt, P., Burns, J., Warner, K., Gouker, P., Healey, P., Wheeler, B., and Keast, C., 2009, "Wafer-Scale 3D Integration of Silicon-on-Insulator RF Amplifiers," IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF '09), San Diego, CA, Jan. 19-21.
104. Chen, C., Chen, C., Wyatt, P., Gouker, P., Burns, J., Knecht, J., Yost, D., Healey, P., and Keast, C., 2008, "Effects of Through-BOX Vias on SOI MOSFETs," IEEE International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA 2008), Hsinchu, Taiwan, Apr. 21-23, pp. 95-96.
105. Chen, C., Chen, C., Burns, J., Yost, D., Warner, K., Knecht, J., Shibles, D., and Keast, C., 2007, "Thermal Effects of Three-Dimensional Integrated Circuit Stacks," IEEE International SOI Conference, Indian Wells, CA, Oct. 1-4, pp. 91-92.
106. Aull, B., Burns, J., Chen, C., Felton, B., Hanson, H., Keast, C., Knecht, J., Loomis, A., Renzi, M., Soares, A., Suntharalingam, V., Warner, K., Wolfson, D., Yost, D., and Young, D., 2006, "Laser Radar Imager Based on 3D Integration of Geiger-Mode Avalanche Photodiodes With Two SOI Timing Circuit Layers," IEEE International Solid-State Circuits Conference (ISSCC 2006), San Francisco, CA, Feb. 6-9, pp. 1179-1188.
107. Chatterjee, R., Fayolle, M., Leduc, P., Pozder, S., Jones, B., Acosta, E., Charlet, B., Enot, T., Heitzmann, M., Zussy, M., Roman, A., Louveau, O., Maitreqean, S., Louis, D., Kernevez, N., Sillon, N., Passemard, G., Pol, V., Mathew, V., Garcia, S., Sparks, T., and Huang, Z., 2007, "Three-Dimensional Chip Stacking Using a Wafer-to-Wafer Integration," IEEE International Interconnect Technology Conference, Burlingame, CA, June 4-6, pp. 81-83.
108. Ledus, P., Crecy, F., Fayolle, M., Fayolle, M., Charlet, B., Enot, T., Zussy, M., Jones, B., Barbe, J., Kernevez, N., Sillon, N., Maitreqean, S., Louis, D., and Passemard, G., 2007, "Challenges for 3D IC Integration: Bonding Quality and Thermal Management," IEEE International Interconnect Technology Conference, Burlingame, CA, June 4-6, pp. 210-212.
109. Poupon, G., Sillon, N., Henry, D., Gillot, C., Mathewson, A., Cioccio, L., Charlet, B., Leduc, P., Vinet, M., and Batude, P., 2009, "System on Wafer: A New Silicon Concept in Sip," Proc. IEEE, 97(1), pp. 60-69.
110. Fujimoto, K., Maeda, N., Kitada, H., Kim, Y., Kawai, A., Arai, K., Nakamura, T., Suzuki, K., and Ohba, T., 2010, "Development of Multi-Stack Process on Wafer-on-Wafer (WoW)," IEEE CPMT Symposium, Tokyo, Japan, Aug. 24-26, pp. 157-160.
111. Lee, C., Yu, A., Yan, L., Wang, H., Han, J., Zhang, Q., and Lau, J. H., 2009, "Characterization of Intermediate In/Ag Layers of Low Temperature Fluxless Solder Based Wafer Bonding for MEMS Packaging," J. Sens. Actuators, A, 154(1), pp. 85-91.
112. Yu, D. Q., Lee, C., Yan, L., Thew, M., and Lau, J. H., 2009, "Characterization and Reliability Study of Low Temperature Hermetic Wafer Level Bonding Using In/Sn Interlayer and Cu/Ni/Au Metallization," J. Alloys Compd., 485(1-2), pp. 444-450.
113. Yu, D. Q., Lee, C., Yan, L. L., Choi, W. K., Yu, A., and Lau, J. H., 2009, "The Role of Ni Buffer Layer on High Yield Low Temperature Hermetic Wafer Bonding Using In/Sn/Cu Metallization," Appl. Phys. Lett., 94(3), p. 034105.
114. Reed, J., Lueck, M., Gregory, C., Huffman, A., Lannon, J., Jr., and Temple, D., 2010, "High-Density Interconnect at 10 μm Pitch With Mechanically Keyed Cu/Sn-Cu and Cu-Cu Bonding for 3-D Integration," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 846-852.
115. Okoro, C., Agarwal, R., Limaye, P., Vandevelde, B., Vandepitte, D., and Beyne, E., 2010, "Insertion Bonding: A Novel Cu-Cu Bonding Approach for 3D Integration," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 1370-1375.
116. Huyghebaert, C., Olmen, J., Chukwudi, O., Coenen, J., Jourdain, A., Cauwenberghe, M., Agarwahl, R., Phommahaxay, R. A., Stucchi, M., and Soussan, P., 2010, "Enabling 10 μm Pitch Hybrid Cu-Cu IC Stacking With Through Silicon Vias," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 1083-1087.
117. Di Cioccio, L., Gueguen, P., Grouiller, E., Vandroux, L., Delaye, V., Rivoire, M., Lugand, J., and Clavelier, L., 2010, "Vertical Metal Interconnect Thanks to Tungsten Direct Bonding," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 1359-1363.
118. Gueguen, P., Di Cioccio, L., Morfouli, P., Zussy, M., Dechamp, J., Bally, L., and Clavelier, L., 2010, "Copper Direct Bonding: An Innovative 3D Interconnect," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 878-883.
119. Taibi, R., Di Cioccio, L., Chappaz, C., Chapelon, L., Gueguen, P., Dechamp, J., Fortunier, R., and Clavelier, L., 2010, "Full Characterization of Cu/Cu Direct Bonding for 3D Integration," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 219-225.
120. Lim, D., Wei, J., Ng, C., and Tan, C., 2010, "Low Temperature Bump-less Cu-Cu Bonding Enhancement With Self Assembled Monolayer (SAM) Passivation for 3-D Integration," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 1364-1369.
121. Yu, D. Q., Li, Y., Lee, C., Choi, W., Thew, S., Foo, C., and Lau, J. H., 2009, "Wafer-Level Hermetic Bonding Using Sn/In and Cu/Ti/Au Metallization," IEEE Trans. CPMT, 32(4), pp. 926-934.
122. Campbell, D., 2010, "Process Characterization Vehicles for 3D Integration," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 1112-1116.
123. Made, R., Gan, C., Yan, L., Yu, A., Yoon, S., Lau, J. H., and Lee, C., 2009, "Study of Low Temperature Thermocompression Bonding in Ag-In Solder for Packaging Applications," J. Electron. Mater., 38(2), pp. 365-371.
124. Pang, X., Chua, T. T., Li, H. Y., Liao, E. B., Lee, W. S., and Che, F. X., 2010, "Characterization and Management of Wafer Stress for Various Pattern Densities in 3D Integration Technology," IEEE 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 1866-1869.
125. Yan, L. L., Lee, C. K., Yu, D. Q., Yu, A., Choi, W., Lau, J. H., and Yoon, S., 2009, "A Hermetic Seal Using Composite Thin Solder In/Sn as Intermediate Layer and Its Interdiffusion Reaction With Cu," J. Electron. Mater., 38(2), pp. 200-207.
126. Lau, J. H., 2010, "Who Invented the TSV (TSV) and When?," posted at 3D InCites on Apr. 24, http://www.semineedle.com/posting/31171
127. Lau, J. H., 2010, "Heart and Soul of 3D IC Integration," posted at 3D InCites on June 29, http://www.semineedle.com/posting/34277
128. Harman, G., 2010, Wire Bonding in Microelectronics, McGraw-Hill, New York.
129. Lau, J. H., 1996, Flip Chip Technology, McGraw-Hill, New York.
130. Lau, J. H., 2000, Low Cost Flip Chip Technologies, McGraw-Hill, New York.
131. Pang, W., Ruby, R., Parker, R., Fisher, P. W., Unkrich, M. A., and Larson, J. D., III, 2008, "A Temperature-Stable Film Bulk Acoustic Wave Oscillator," IEEE Electron Device Lett., 29(4), pp. 315-318.
132. Small, M., Ruby, R., Ortiz, S., Parker, R., Zhang, F., Shi, J., and Otis, B., 2011, "Wafer-Scale Packaging for FBAR-Based Oscillators," Joint Conference of the IEEE International Frequency Control and the European Frequency and Time Forum (FCS), San Francisco, CA, May 2-5.
133. Wakabayashi, H., Yamaguchi, H. K., Okano, M., Kuramochi, S., Kumagai, O., Sakane, S., Ito, M., Hatano, M., Kikuchi, M., Yamagata, Y., Shikanai, T., Koseki, K., Mabuchi, K., Maruyama, Y., Akiyama, K., Miyata, E., Honda, T., and Ohashi, M., 2010, "A 1/2.3-Inch 10.3M Pixel 50 Frame/s Back-Illuminated CMOS Image Sensor," IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, CA, Feb. 7-11, pp. 411-412.
134. Sukegawa, S., Umebayashi, T., Nakajima, T., Kawanobe, H., Koseki, K., Hirota, I., Haruta, T., Kasai, M., Fukumoto, K., Wakano, T., Inoue, K., Takahashi, H., Nagano, T., Nitta, Y., Hirayama, T., and Fukushima, N., 2013, "A 1/4-Inch 8M Pixel Back-Illuminated Stacked CMOS Image Sensor," IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, CA, Feb. 17-21, pp. 484-484.
135. Gat, A., Gerzberg, L., Gibbons, J., Mages, T., Peng, J., and Hong, J., 1978, "CW Laser of Polyerystalline Silicon: Crystalline Structure and Electrical Properties," Appl. Phys. Lett., 33(8), pp. 775-778.
136. Tuckerman, D. B., Bauer, L. O., Brathwaite, N. E., Demmin, J., Flatow, K., Hsu, R., Kim, P., Lin, C. M., Lin, K., Nguyen, S., and Thipphavong, V., 1994, "Laminated Memory: A New Three-Dimensional Packaging Technology for MCMs," IEEE Multi-Chip Module Conference (MCMC-94), Santa Cruz, CA, Mar. 15-17, pp. 58-63.
137. Lim, S., Rao, V., Hnin, W., Ching, W., Kripesh, V., Lee, C., Lau, J. H., Milla, J., and Fenner, A., 2008, "Process Development and Reliability of Microbumps," IEEE Electronic Packaging Technology Conference (EPTC 2008), Singapore, Dec. 9-12, pp. 367-372.
138. Sutanto, J., 2012, "POSSUM™ Die Design as a Low Cost 3D Packaging Alternative," 3D Packaging, 25, pp. 16-18.
139. Yoon, S., Caparas, J., Lin, Y., and Marimuthu, P., 2012, "Advanced Low Profile PoP Solution With Embedded Wafer Level PoP (eWLB-PoP) Technology," IEEE 62nd Electronic Components and Technology Conference (ECTC), San Diego, CA, May 29-June 1, pp. 1250-1254.
140. Graham, S., 2013, "Development of Hybrid Memory Cube," 3D IC Panel Discussion, IMAPS 46th International Symposium on Microelectronics, Orlando, FL, Sept. 30-Oct. 3.
141. JEDEC, 2011, "Standard No. JESD229, Wide I/O Single Data Rate (Wide I/O SDR)," and "Standard No. JESD229-2, Wide I/O 2 (WideI/O2)," JEDEC, Arlington, VA.
142. JEDEC, 2013, "Standard No. JESD235, High Bandwidth Memory (HBM) DRAM," JEDEC, Arlington, VA.
143. Brunnbauer, M., Fürgut, E., Beer, G., Meyer, T., Hedler, H., Belonio, J., Nomura, E., Kiuchi, K., and Kobayashi, K., 2006, "An Embedded Device Technology Based on a Molded Reconfigured Wafer," IEEE 56th Electronic Components and Technology Conference (ECTC), San Diego, CA, May 30-June 2, pp. 547-551.
144. Brunnbauer, M., Furgut, E., Beer, G., and Meyer, T., 2006, "Embedded Wafer Level Ball Grid Array (eWLB)," IEEE 8th Electronics Packaging Technology Conference (EPTC '06), Singapore, Dec. 6-8.
145. Meyer, T., Ofner, G., Bradl, S., Brunnbauer, M., and Hagen, R., 2008, "Embedded Wafer Level Ball Grid Array (eWLB)," IEEE 10th Electronics Packaging Technology Conference (EPTC 2008), Singapore, Dec. 9-12, pp. 994-998.
146. Brunnbauer, M., Meyer, T., Ofner, G., Mueller, K., and Hagen, R., 2008, "Embedded Wafer Level Ball Grid Array (eWLB)," 33rd IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT), Penang, Malaysia, Nov. 4-6.
147. Pressel, K., Beer, G., Meyer, T., Wojnowski, M., Fink, M., Ofner, G., and Römer, B., 2010, "Embedded Wafer Level Ball Grid Array (eWLB) Technology for System Integration," IEEE CPMT Symposium, Tokyo, Japan, Aug. 24-26.
148. Keser, B., Amrine, C., Duong, T., Fay, O., Hayes, S., Leal, G., Lytle, W., Mitchell, D., and Wenzel, R., 2007, "The Redistributed Chip Package: A Breakthrough for Advanced Packaging," IEEE 57th Electronic Components and Technology Conference (ECTC '07), Reno, NV, May 29-June 1, pp. 286-291.
149. Hayes, S., Chhabra, N., Duong, T., Gong, Z., Mitchell, D., and Wright, J., 2011, "System-in-Package Opportunities With the Redistributed Chip Package (RCP)," 8th Annual International Wafer-Level Packaging Conference (IWLPC 2011), Santa Clara, CA, Oct. 3-6, pp. 10.1-10.7.
150. Chaabouni, H., Rousseau, M., Ldeus, P., Farcy, A., El Farhane, R., Thuaire, A., Haury, G., Valentian, A., Billot, G., Assous, M., de Crecy, F., Cluzel, J., Toffoli, A., Bounchu, D., Cadix, L., Lacrevaz, T., Ancey, P., Sillon, N., and Flechet, B., 2010, "Investigation on TSV Impact on 65nm CMOS Devices and Circuits," IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 6-8, pp. 35.1.1-35.1.4.