Study on the effect of wafer back grinding process on nanomechanical behavior of multilayered low-k stack

IEEE Transactions on Components, Packaging and Manufacturing Technology

Volumn 2, Issue 1, 2012, Pages 3-12

  Sekhar, Vasarla Nagendra ^a   Shen, Lu ^b   Kumar, Aditya ^c   Chai, Tai Chong ^a   Zhang, Xiaowu ^a   Premchandran, C S ^c   Kripesh, Vaidyanathan ^a   Yoon, Seung Wook ^d   Lau, John H ^e  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b INSTITUTE OF MATERIALS RESEARCH AND ENGINEERING   (Singapore)

^c GLOBALFOUNDRIES   (Singapore)

^d STATS CHIPPAC LTD   (Singapore)

^e INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

3 D packaging; low k stack; nanoindentation; nanoscratch; transmission electron microscopy analysis; wafer back grinding wafer thinning

Indexed keywords

3D PACKAGING; LOW-K STACK; NANO-SCRATCH; TRANSMISSION ELECTRON MICROSCOPY ANALYSIS; WAFER BACK GRINDING/WAFER THINNING;

FRACTURE; GRINDING (MACHINING); MECHANICAL PROPERTIES; NANOINDENTATION; NANOTECHNOLOGY; STRESSES; TRANSMISSION ELECTRON MICROSCOPY;

ELECTRONICS PACKAGING;

EID: 84859085195     PISSN: 21563950     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCPMT.2011.2141989     Document Type: Article

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