Redistribution layers (RDLs) for 2.5D/3D IC integration

Journal of Microelectronics and Electronic Packaging

Volumn 11, Issue 1, 2014, Pages 16-24

  Lau, J ^a   Tzeng, P ^a   Lee, C ^a   Zhan, C ^a   Li, M ^b   Cline, J ^b   Saito, K ^b   Hsin, Y ^a   Chang, P ^a   Chang, Y ^a   Chen, J ^a   Chen, S ^a   Wu, C ^a   Chang, H ^a   Chien, C ^a   Lin, C ^a   Ku, T ^a   Lo, R ^a   Kao, M ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^b RAMBUS INC   (United States)

Author keywords

3D IC integration; Cu damascene; Polymer; Redistribution layer (RDL); Through silicon via (TSV)

Indexed keywords

INTEGRATED CIRCUITS; INTEGRATION; POLYMERS; TIMING CIRCUITS;

BACK END OF LINES; CU DAMASCENE; CU PLATINGS; INTEGRAL PART; MATERIALS AND PROCESS; METAL LAYER; REDISTRIBUTION LAYERS; THROUGH-SILICON-VIA (TSV);

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 84974651381     PISSN: 15514897     EISSN: None     Source Type: Journal    
DOI: 10.4071/imaps.406     Document Type: Conference Paper

References (20)

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