Development of an optimized power delivery system for 3D IC integration with TSV silicon interposer

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2012, Pages 678-682

  Li, Zhe ^a   Shi, Hong ^a   Xie, John ^a   Rahman, Arif ^a  

^a ALTERA CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3D SYSTEMS; DE-COUPLING CAPACITANCE; ELECTRICAL PERFORMANCE; ENGINEERING EVALUATIONS; IMPEDANCE CHARACTERISTICS; LOSS MECHANISMS; LOWER-POWER CONSUMPTION; MICRO-BUMPS; MIM CAPACITORS; MULTI-CHIP; PERFORMANCE IMPACT; PHYSICAL INTERFACE; POWER DELIVERY NETWORK; POWER DELIVERY SYSTEMS; RE-DISTRIBUTION; TEST VEHICLE; THROUGH-SILICON-VIA; WIRING DENSITY;

ELECTRIC POWER TRANSMISSION; MIM DEVICES; OPTIMIZATION; THREE DIMENSIONAL COMPUTER GRAPHICS;

INTEGRATION;

EID: 84866878729     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2012.6248905     Document Type: Conference Paper

References (5)

1. Knickerbocker, J.U., et al "3-D silicon intergration and silicon packaging technology using silicon through-vias," IEEE Journal of Solid-State Circuits, Vol. 41, No.8 (2006), page 1718- 1725
2. R. R. Tummala, M. Swaminathan, "Introduction to System-on-Package (SOP) Miniaturization of the Entire System", McGraw-Hill (2008)
3. th Electronic Componenets and Technology Conf, Las Vegas, USA, 2010, page 1455-1460
4. Larry Smith, Zhe Li, et al "On-Die Capacitance Measurement and Impact o Product Performance" DesignCon 2011
5. Zhe Li, Hong Shi, "Analysis of FPGA PDN Noise Propagation by Die/Package 3D Modeling" DesignCon 2010