Thermal performance of 3D IC integration with Through-Silicon Via (TSV)

Journal of Microelectronics and Electronic Packaging

Volumn 9, Issue 2, 2012, Pages 97-103

  Chien, Heng Chieh ^a   Lau, John H ^a   Chao, Yu Lin ^a   Tain, Ra Min ^a   Dai, Ming Ji ^a   Wu, Sheng Tsai ^a   Lo, Wei Chung ^a   Kao, Ming Jer ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

3D IC integration; Equivalent thermal conductivities of Cu filled TSVs; SiO2; Through silicon via (TSV)

Indexed keywords

EQUIVALENT THERMAL CONDUCTIVITIES; HEAT TRANSFER SIMULATION; INTEGRATION STRUCTURES; SIO2; THERMAL BEHAVIORS; THERMAL PERFORMANCE; THROUGH-SILICON VIA; THROUGH-SILICON-VIA (TSV);

INTEGRATED CIRCUIT MANUFACTURE; INTEGRATION; THREE DIMENSIONAL;

THERMAL CONDUCTIVITY;

EID: 84883439460     PISSN: 15514897     EISSN: None     Source Type: Journal    
DOI: 10.4071/imaps.309     Document Type: Article

References (19)

1. M. Groger. S.M. ilarb. D. Morris, W. Eisenstadt, and S. Puligundla. "High speed I/O and thermal effect characterization of 3D stacked lCs," Proceedings of IEEE International Conference on Digital Object Identifier. pp. 1-5. 2009.
2. T. Hung. M. Yew. C. Chou, and K. Chiang, "A study of thermal performance for chip-in-substrate package on package." Proceedings of Microelectronics and Packaging Conference, pp. 1-6, 2009.
3. H. Oprins. V. Cherman, C. Torregiani, M. Stucchi. B. Vandevelde. and E. Beyne. "Thermal test vehicle for the validation of thermal modelling of hot spot dissipation in 3D stacked IC's." Proceedings of Electronic System-Integration Technology Conference, pp. 1-6. 2010.
4. H. Oprins and V. Cherman. V.M. Stucchi. B. Vandevelde. G. Van der Plas, P. Marehal, and E. Beyne. "Steady state and transient thermal analysis of hot spots in 3D stacked IC's using dedicated test chips." Proceedings of Semiconductor Thermal Measurement and Management Symposium, pp. 131-137, 2011.
5. A. Jain, "Thermal characteristics of multi-die, three-dimensional integrated circuits with unequally sized die," Proceedings of Thermal and Thermomechanical Phenomena in Electronic Systems, pp. 1-6, 2010.
6. A. Jain. R. Jones. R. Chatterjee. and S. Pozder. "Analytical and numerical modeling of the thermal performance of three-dimensional integrated circuits," IEEE Transactions on Components and Packaging Technologies. Vol. 33, No. I, pp. 56-63. 2010.
7. P. Leduca. F. de Crecy. M. Fayolle, B. Charlet. T. Enot. M. Zussy. B. Jones, J.-C. Barbe, N. Kernevez. N. Sillon, S. Maitrejean, and D. Louisa, "Challenges for 3D IC integration: Bonding quality and thermal management," Proceedings of International Interconnect Technology Conference, pp. 210-212. 2007.
8. M. Hsieh, C. Yu. and S. Wu. "Thermo-mechanical simulative study for 3D vertical stacked IC packages with spacer structures." Proceedings of Semiconductor Thermal Measurement and Management Svmposium. pp. 47-54. 2010.
9. A. Yu. N. Khan. G. Archit. D. Pinjalal. K. Toh. V. Kripesh. S. Yoon. and J.H. Lau. "Dev elopment of silicon carriers with embedded thermal solutions for high power 3-D package," IEEE Transactions on Components and Packaging Technology, Vol. 32, No. 3, pp. 566-571. 2009.
10. J.H. Lau and G. Tang, "Thermal management of 3D IC integration with TSV (through silicon via)." IEEE Proceedings of ECTC. pp. 635-640. 2009.
11. N. Khan. L. Yu. P. Tan. S. Ho. N. Su. H. Wai. K. Vaidyanathan. D. Pinjala, J.H. Lau. and T. Chuan. "3D Packaging with through silicon via (TSV) for electrical and fluidie interconnections." IEEE Proceedings of ECTC, pp. 1153-1158. 2009.
12. G. Hoe, G. Tang, P. Damaruganath, C. Chong. J.H. Lau. X. Zhang, and K. Vaidyanathan, "Effect of TSV interposer on the thermal performance of FCBGA package." IEEE Proceedings of Electronics Packaging and Technology Conference, pp. 778-786, 2009.
13. J.H. Lau. T.G. Yue, G.Y.Y. Hoc. X.W. Zhang. C.T. Chong. P. Damaruganath, and K. Vaidyanathan. "Effects of TSV (through silicon via) interposer chip on the thermal performances of 3-D IC packaging." ASMF. Paper no. IPACK2009-89380.
14. G. Tang. (). Navas, D. Pinjala. J.H. Lau. A. Yu. and V. Kripesh. "Integrated liquid cooling systems for 3-D slacked TSV modules." IEEE Transactions on Components and Packaging Technologies. Vol. 33, No. 1. pp. 184-195, 2010.
15. J.H. Lau, C.K. Lee. C.S. Premaehandran, and A. Yu. Advanced MF.MS Packaging. McGraw-Hill. New York. 2010.
16. J.H. Lau, "Reliability of RoHS Compliant 2D & 3D IC Interconnects," McGraw-Hill, New York, 2011.
17. H.-C. Chien. Y.-L. Chao, J.H. Lau. R.-M. Tain. M.-J. Dai. P.J. Tzemi. C.-H. Lin. Y.-C. Hsin. S.-C. Chen. J.-C. Chien. C.-C. Chen. C.-H. Ho. W.-C. Lo. T.-K. Ku. and M.-J. Kao. "A thermal performance measurement method for blind through silicon vias (TSVs) in a 300 mm wafer." Proceedings of the IEEE ECTC. pp. 1204-1210. 2011.
18. J.H. Lau, H.C. Chien, and R. Tain. "TSV inlerposers with embedded microchannels for 3D IC and multiple high-power LEDs integration SiP." ASME Paper no. InterPACK2011-52204.
19. J.H. Lau. Y.S. Chan, and S.R. Lee, "Thermal-enhanced and cost-effective 3D IC integration with TSV (through-silicon via) mterposers for high-performance applications." ASMF Paper no. IMECE2010-40975.