Impact of post-plating anneal and through-silicon via dimensions on Cu pumping

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2013, Pages 586-591

  De Messemaeker, Joke ^a   Pedreira, Olalla Varela ^a   Vandevelde, Bart ^a   Philipsen, Harold ^a   De Wolf, Ingrid ^a   Beyne, Eric ^a   Croes, Kristof ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEAL TEMPERATURES; BACK END OF LINES; CU PLATINGS; HIGH-TEMPERATURE PROCESSING; OPTICAL PROFILOMETRY; RELIABILITY RISKS; THROUGH SILICON VIAS; THROUGH-SILICON VIA;

ELECTRONICS PACKAGING; PLATING; RELIABILITY; SINTERING;

PUMPS;

EID: 84883330481     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2013.6575633     Document Type: Conference Paper

References (6)

1. A. Mercha et al., "Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k/metal gate CMOS performance", 2010 International Electron Devices Meeting (IEEE, 2010), pp. 2.2.1-2.2.4
2. J. Van Olmen et al., "3D stacked IC demonstration using a through silicon via first approach", 2008 International Electron Devices Meeting (IEEE, 2008), pp. 1-4
3. C. Okoro et al., "Elimination of the axial deformation problem of Cu-TSV in 3D integration", in Stress-induced phenomena in metallization: 11th international workshop, Dresden, Germany, April 12-14, 2010, 214-220D
4. I. De Wolf et al., "Cu pumping in TSVs: Effect of pre-CMP thermal budget", Microelectronics Reliability, vol. 51, no. 9-11, pp. 1856-1859, 2011
5. A. Heryanto et al., "Effect of copper TSV annealing on via protrusion for TSV wafer fabrication", Journal of Electronic Materials, vol. 41, no. 9, pp. 2533-2542, 2012
6. F. Che, "Numerical and experimental study on Cu protrusion of Cu-filled through-silicon vias (TSV)", 3rd IEEE International 3D System Integration Conference (3DIC), P1-1-13 (6 ps.), 2011.