An electrical testing method for blind through silicon vias (TSVs) for 3D IC integration

Journal of Microelectronics and Electronic Packaging

Volumn 8, Issue 4, 2011, Pages 140-145

  Sheu, Shyh Shyuan ^a,b   Lin, Zhe Hui ^a   Hung, Jui Feng ^a   Lau, John H ^a   Chen, Peng Shu ^a   Wu, Shih Hsien ^a,b   Su, Keng Li ^a   Lin, Chih Sheng ^a   Lai, Shinn Juh ^a   Cheng, Kuo Hsing ^b   Ku, Tzu Kun ^a   Lo, Wei Chung ^a   Kao, Ming Jer ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^b NATIONAL CENTRAL UNIVERSITY   (Taiwan)

Author keywords

3D IC integration; Through silicon via (TSV); TSV electrical testing method and guidelines

Indexed keywords

COORDINATION REACTIONS; ELECTRIC VARIABLES MEASUREMENT; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT INTERCONNECTS; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATION; INTEGRATION TESTING; SCATTERING PARAMETERS; SILICON OXIDES; TESTING; TIMING CIRCUITS;

COMPONENT TESTING; ELECTRICAL TESTING; HIGH-FREQUENCY COUPLINGS; PARASITIC PARAMETER; TECHNOLOGICAL CONDITIONS; TESTING APPARATUS; THROUGH SILICON VIAS; THROUGH-SILICON-VIA (TSV);

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 84880302962     PISSN: 15514897     EISSN: None     Source Type: Journal    
DOI: 10.4071/imaps.307     Document Type: Article

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