Through-Silicon Hole Interposers for 3-D IC Integration

IEEE Transactions on Components, Packaging and Manufacturing Technology

Volumn 4, Issue 9, 2014, Pages 1407-1419

  Lau, John H ^a   Lee, Ching Kuan ^a   Zhan, Chau Jie ^a   Wu, Sheng Tsai ^a   Chao, Yu Lin ^a   Dai, Ming Ji ^a   Tain, Ra Min ^a   Chien, Heng Chieh ^a   Hung, Jui Feng ^a   Chien, Chun Hsien ^a   Cheng, Ren Shing ^a   Huang, Yu Wei ^a   Cheng, Yu Mei ^a   Liao, Li Ling ^a   Lo, Wei Chung ^a   Kao, Ming Jer ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

2.5D 3D IC integration; interposer; re distribution layer; through silicon hole; through silicon via

Indexed keywords

AUTOMOBILE MANUFACTURE; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT INTERCONNECTS; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATION; SILICON; THREE DIMENSIONAL INTEGRATED CIRCUITS;

FINAL ASSEMBLY; INTERPOSER; RE-DISTRIBUTION; SIP TECHNOLOGY; TEST VEHICLE; THERMAL CYCLING TEST; THROUGH-SILICON HOLE; THROUGH-SILICON-VIA;

SYSTEM-IN-PACKAGE;

EID: 84960437799     PISSN: 21563950     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCPMT.2014.2339832     Document Type: Article

References (25)

1. J. H. Lau, Through-Silicon via for 3D Integration. New York, NY, USA: McGraw-Hill, 2013.
2. J. H. Lau, Reliability of ROHS-Compliant 2D and 3D IC Integration. New York, NY, USA: McGraw-Hill, 2011.
3. J. H. Lau, C. K. Lee, C. S. Premachandran, A. Yu, Advanced MEMS Packaging. New York, NY, USA: McGraw-Hill, 2010.
4. B. Banijamali, S. Ramalingam, K. Nagarajan, R. Chaware, "Advanced reliability study of TSV interposers and interconnects for the 28 nm technology FPGA," in Proc. 61st IEEE/ECTC, Orlando, FL, USA, Jun. 2011, pp. 285-290.
5. R. Chaware, K. Nagarajan, S. Ramalingam, "Assembly and reliability challenges in 3D integration of 28 nm FPGA die on a large high density 65 nm passive interposer," in Proc. 62nd IEEE/ECTC, San Diego, CA, USA, May 2012, pp. 279-283.
6. B. Banijamali, S. Ramalingam, H. Liu, M. Kim, "Outstanding and innovative reliability study of 3D TSV interposer and fine pitch solder micro-bumps," in Proc. 62nd IEEE/ECTC, May/Jun. 2012, pp. 309-314.
7. J. Xie et al., "Enabling the 2.5D integration," in Proc. IMAPS Int. Symp. Microelectron., San Diego, CA, USA, Sep. 2012, pp. 254-267.
8. Z. Li, H. Shi, J. Xie, A. Rahman, "Development of an optimized power delivery system for 3D IC integration with TSV silicon interposer," in Proc. 62nd IEEE/ECTC, San Diego, CA, USA, May 2012, pp. 678-682.
9. B. Banijamali et al., "Reliability evaluation of a CoWoS-enabled 3D IC package," in Proc. 63rd IEEE/ECTC, May 2013, pp. 35-40.
10. L. Lin et al., "Reliability characterization of chip-on-wafer-on-substrate (CoWoS) 3D IC integration technology," in Proc. 63rd IEEE/ECTC, Las Vegas, NV, USA, May 2013, pp. 366-371.
11. Y.-L. Chuang et al., "Unified methodology for heterogeneous integration with CoWoS technology," in Proc. 63rd IEEE/ECTC, San Diego, CA, USA, May 2013, pp. 852-859.
12. W. Kwon et al., "Enabling a manufacturable 3D technologies and ecosystem using 28 nm FPGA with stack silicon interconnect technology," in Proc. IMAPS Int. Symp. Microelectron., Oct. 2013, pp. 217-222.
13. L. Li et al., "Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration," in Proc. 62nd IEEE/ECTC, San Diego, CA, USA, May/Jun. 2012, pp. 1040-1046.
14. H.-C. Chien et al., "Thermal evaluation and analyses of 3D IC integration SiP with TSVs for network system applications," in Proc. 62nd IEEE/ECTC, San Diego, CA, USA, May/Jun. 2012, pp. 1866-1873.
15. S. T. Wu, J. H. Lau, H. Chien, "Nonlinear thermal stress and creep strain analyses of a 3D IC integration SiP with TSVs for network system application," in Proc. IEEE ICEP, Apr. 2012, pp. 681-688.
16. S. T.Wu et al., "Thermal stress and creep strain analyses of a 3D IC integration SiP with passive interposer for network system application," in Proc. 45th IMAPS Int. Symp. Microelectron., Sep. 2012, pp. 1038-1045.
17. H. C. Chien, J. H. Lau, T. Chao, M. Dai, R. Tain, "Thermal management of Moore's law chips on both sides of an interposer for 3D IC integration SiP," in Proc. IEEE ICEP, Apr. 2012, pp. 38-44.
18. J. H. Lau et al., "Large size silicon interposer and 3D IC integration for system-in-packaging (SiP)," in Proc. 45th IMAPS Int. Symp. Microelectron., Sep. 2012, pp. 1209-1214.
19. M. Ji et al., "3D Si interposer design and electrical performance study," in Proc. DesignCon, Santa Clara, CA, USA, Jan. 2013, 1-WA2, pp. 1-23.
20. S.-T. Wu, H.-C. Chien, J. H. Lau, M. Li, J. Cline, M. Ji, "Thermal and mechanical design and analysis of 3D IC interposer with doublesided active chips," in Proc. 63rd IEEE/ECTC, Las Vegas, NV, USA, May 2013, pp. 1471-1479.
21. P.-J. Tzeng et al., "Process integration of 3D Si interposer with doublesided active chip attachments," in Proc. 63rd IEEE/ECTC, Las Vegas, NV, USA, May 2013, pp. 86-93.
22. J. H. Lau et al., "Redistribution layers (RDLs) for 2.5D/3D IC integration," IMAPS Trans. J. Microelectron. Packag., vol. 11, no. 1, pp. 16-24, 2014.
23. S.-T. Wu et al., "Ultra low-cost through-silicon holes (TSHs) interposers for 3D IC integration SiPs," in Proc. 62nd IEEE/ECTC, San Diego, CA, USA, May 2012, pp. 1618-1624.
24. J. F. Hung et al., "Electrical performance of through-silicon vias (TSVs) for high-frequency 3D IC integration applications," in Proc. 45th IMAPS Int. Symp. Microelectron., Sep. 2012, pp. 1221-1228.
25. Board Level Drop Test Method of Components for Handheld Electronic Products, JEDEC Standard JESD22-B111, Jul. 2003.