Investigation on TSV impact on 65nm CMOS devices and circuits

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2010, Pages

  Chaabouni, H ^a,b   Rousseau, M ^a,c   Leduc, Patrick ^a   Farcy, A ^c   El Farhane, R ^a   Thuaire, A ^a   Haury, G ^c   Valentian, A ^a   Billiot, G ^a   Assous, M ^a   De Crecy, F ^a   Cluzel, J ^a   Toffoli, A ^a   Bouchu, D ^a   Cadix, L ^b,c   Lacrevaz, T ^b   Ancey, P ^c   Sillon, N ^a   Flechet, B ^b  

^a CEA GRENOBLE   (France)

^b UNIVERSITÉ DE SAVOIE   (France)

^c STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS DEVICES; ELECTRICAL COUPLING; ELECTRICAL TESTS; MECHANICAL IMPACTS; MODELING RESULTS; MOS-FET; RING OSCILLATOR; THREE DIMENSIONAL (3D) INTEGRATION; THROUGH SILICON VIAS;

DRAIN CURRENT; ELECTRON DEVICES; MOSFET DEVICES; THREE DIMENSIONAL;

OSCILLATORS (ELECTRONIC);

EID: 79951835632     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2010.5703479     Document Type: Conference Paper

References (5)

1. Yang Y. & al, "Electrical evaluation of 130-nm MOSFETs with TSV proximity in 3D-SIC structure" IITC Proc., Burlingame, California, USA, June 2010.
2. Marchal A. & al, "Verifying thermal/thermo-mechanical behavior of 3D stack - Challenges and Solutions, VLSI Technology Proc., Honolulu, Hawaï, USA, June 2010.
3. Cadix L. & al., "Integration and frequency dependent parametric modeling of Through Silicon Via involved in high density 3D chip stacking", ECS meeting, Las Vegas, October 2010 (to be published)
4. Zoberbier M. & al. "300 nm Lithography and bonding technologies for TSV applications in image sensor and memory products", http://www.suss.com/service/technical-publications
5. Matsuda K. & al, "Nonlinear piezoresistance effects in silcion" J. Appl. Phys., Vol.73, N° 4, Feb.1993