Low-cost and low-loss 3D silicon interposer for high bandwidth logic-to-memory interconnections without TSV in the logic IC

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2012, Pages 292-297

  Sundaram, Venky ^a   Chen, Qiao ^a   Suzuki, Yuya ^b   Kumar, Gokul ^a   Liu, Fuhan ^a   Tummala, Rao ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b ZEON CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

3-D ICS; CHIP-TO-CHIP INTERCONNECTIONS; CPW LINE; DRY FILMS; ELECTRICAL CHARACTERIZATION; ELECTRICAL PERFORMANCE; EQUIVALENT BANDWIDTH; FINE PITCH; HIGH BANDWIDTH; HIGH THROUGHPUT; LASER PROCESS; LOGIC IC; LOW COSTS; NON-TRADITIONAL; POLYMER LINERS; SCALABLE APPROACH; TESTABILITY;

BANDWIDTH; COSTS; POLYMERS; POLYSILICON; THREE DIMENSIONAL COMPUTER GRAPHICS;

SILICON WAFERS;

EID: 84866318234     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2012.6248844     Document Type: Conference Paper

References (5)

1. Patrick Dorsey, "Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency", White Paper, www.xilinx.com
2. Kumar, G.; Bandyopadhyay, T.; Sukumaran, V.; Sundaram, V.; Sung Kyu Lim; Tummala, R.; "Ultra-high I/O density glass/silicon interposers for high bandwidth smart mobile applications", Proceedings of the 61st IEEE ECTC Conference, pp. 217-223, 2011.
3. M. Sunohara, et al., "Silicon interposer with TSVs (through silicon vias) and fine multilayer wiring," in Proceedings of the 58th Electronic Components and Technology Conference, 2008, pp. 847-852.
4. Knickerbocker, J.U.; Patel, C.S.; Andry, P.S.; Tsang, C.K.; Buchwalter, L.P.; Sprogis, E.J.; Hua Gan; Horton, R.R.; Polastre, R.J.; Wright, S.L.; Cotte, J.M.; "3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias", IEEE Journal of Solid-State Circuits, Vol. 41, Issue 8, pp. 1718-1725, 2006.
5. Qiao Chen; Bandyopadhyay, T.; Suzuki, Y.; Fuhan Liu; Sundaram, V.; Pucha, R.; Swaminathan, M.; Tummala, R; "Design and demonstration of low cost, panel-based polycrystalline silicon interposer with through-package-vias (TPVs)", Proceedings of the 61st IEEE ECTC Conference, pp. 855-860, 2011.