-
1
-
-
61649092607
-
Fabrication and characterization of robust through-silicon vias for silicon-carrier applications
-
P.S. Andry, C.K. Tsang, B.C. Webb, E.J. Sprogis, S.L. Wright, and B. Bang Fabrication and characterization of robust through-silicon vias for silicon-carrier applications IBM J Res Dev 52 6 2008 571 581
-
(2008)
IBM J Res Dev
, vol.52
, Issue.6
, pp. 571-581
-
-
Andry, P.S.1
Tsang, C.K.2
Webb, B.C.3
Sprogis, E.J.4
Wright, S.L.5
Bang, B.6
-
2
-
-
51349137210
-
3-D silicon integration
-
May
-
Knickerbocker JU, Andry PS, Dang B, Horton RR, Patel CS, Polastre RJ, et al. 3-D silicon integration. In: IEEE proceedings of electronic components and technology conf; May 2008. p. 538-43.
-
(2008)
IEEE Proceedings of Electronic Components and Technology Conf
, pp. 538-543
-
-
Knickerbocker, J.U.1
Andry, P.S.2
Dang, B.3
Horton, R.R.4
Patel, C.S.5
Polastre, R.J.6
-
3
-
-
51349119303
-
A silicon interposer BGA package with Cu-filled TSV and multi-layer Cu-plating interconnection
-
Orlando, FL; May
-
Kumagai K, Yoneda Y, Izumino H, Shimojo H, Sunohara M, Kurihara T. A silicon interposer BGA package with Cu-filled TSV and multi-layer Cu-plating interconnection. In: IEEE proceedings of electronic components and technology conf, Orlando, FL; May 2008. p. 571-6.
-
(2008)
IEEE Proceedings of Electronic Components and Technology Conf
, pp. 571-576
-
-
Kumagai, K.1
Yoneda, Y.2
Izumino, H.3
Shimojo, H.4
Sunohara, M.5
Kurihara, T.6
-
4
-
-
51349111449
-
Silicon interposer with TSVs (Through Silicon Vias) and fine multilayer wiring
-
Orlando, FL; May
-
Sunohara M, Tokunaga T, Kurihara T, Higashi M. Silicon interposer with TSVs (Through Silicon Vias) and fine multilayer wiring. In: IEEE proceedings of electronic components and technology conf, Orlando, FL; May 2008. p. 847-52.
-
(2008)
IEEE Proceedings of Electronic Components and Technology Conf
, pp. 847-852
-
-
Sunohara, M.1
Tokunaga, T.2
Kurihara, T.3
Higashi, M.4
-
5
-
-
35348877852
-
Power delivery network design for 3D SIP integrated over silicon interposer platform
-
Reno, NV; May
-
Lee HS, Choi Y-S, Song E, Choi K, Cho T, Kang S. Power delivery network design for 3D SIP integrated over silicon interposer platform. In: IEEE proceedings of electronic components and technology conf, Reno, NV; May 2007. p. 1193-8.
-
(2007)
IEEE Proceedings of Electronic Components and Technology Conf
, pp. 1193-1198
-
-
Lee, H.S.1
Choi, Y.-S.2
Song, E.3
Choi, K.4
Cho, T.5
Kang, S.6
-
7
-
-
51349168308
-
Nonlinear thermal stress/strain analysis of copper filled TSV (Through Silicon Via) and their flip-chip microbumps
-
Orlando, FL; May
-
Selvanayagam C, Lau JH, Zhang X, Seah S, Vaidyanathan K, Chai T. Nonlinear thermal stress/strain analysis of copper filled TSV (Through Silicon Via) and their flip-chip microbumps. In: IEEE proceedings of electronic components and technology conf, Orlando, FL; May 2008. p. 1073-81.
-
(2008)
IEEE Proceedings of Electronic Components and Technology Conf
, pp. 1073-1081
-
-
Selvanayagam, C.1
Lau, J.H.2
Zhang, X.3
Seah, S.4
Vaidyanathan, K.5
Chai, T.6
-
8
-
-
33845581077
-
Effective thermal via and decoupling capacitor insertion for 3D system-on-package
-
San Siego, CA; May
-
Eric Wong, Jacob Minz, Sung Kyu Lim. Effective thermal via and decoupling capacitor insertion for 3D system-on-package. In: IEEE proceedings of electronic components and technology conf, San Siego, CA; May 2006. p. 1795-801.
-
(2006)
IEEE Proceedings of Electronic Components and Technology Conf
, pp. 1795-1801
-
-
Wong, E.1
Minz, J.2
Sung, K.L.3
-
12
-
-
84856484569
-
Design and process of 3D MEMS system-in-package (SiP)
-
J.H. Lau Design and process of 3D MEMS system-in-package (SiP) IMAPS Trans, J Microelectron Electron Pack First Quarter Issue 2010 10 15
-
(2010)
IMAPS Trans, J Microelectron Electron Pack
, pp. 10-15
-
-
Lau, J.H.1
-
13
-
-
77952599293
-
3D LED and IC wafer level packaging
-
J.H. Lau, R. Lee, M. Yuen, and P. Chan 3D LED and IC wafer level packaging J Microelectron Int 27 2 2010 98 105
-
(2010)
J Microelectron Int
, vol.27
, Issue.2
, pp. 98-105
-
-
Lau, J.H.1
Lee, R.2
Yuen, M.3
Chan, P.4
-
14
-
-
79951892774
-
State-of-the-art and trends in 3D integration
-
MARCH/APRIL
-
J.H. Lau State-of-the-art and trends in 3D integration Chip Scale Rev March/April 2010 22 28
-
(2010)
Chip Scale Rev
, pp. 22-28
-
-
Lau, J.H.1
-
15
-
-
79951910180
-
3D IC integration with TSV interposers for high-performance applications
-
SEPTEMBER/OCTOBER
-
J.H. Lau, Y.S. Chan, and R.S.W. Lee 3D IC integration with TSV interposers for high-performance applications Chip Scale Rev September/October 2010 26 29
-
(2010)
Chip Scale Rev
, pp. 26-29
-
-
Lau, J.H.1
Chan, Y.S.2
Lee, R.S.W.3
-
16
-
-
79956077641
-
Overview of TSV and 3D IC integration
-
J.H. Lau Overview of TSV and 3D IC integration J Microelectron Int 28 2 2011 8 22
-
(2011)
J Microelectron Int
, vol.28
, Issue.2
, pp. 8-22
-
-
Lau, J.H.1
-
17
-
-
70349659227
-
Three dimensional interconnects with high aspect ratio TSVs and fine pitch solder microbumps
-
San Diego, CA; May IEEE transactions in advanced packaging, in press
-
Yu A, Lau JH, Ho S, Kumar A, Yin H, Ching J, et al. Three dimensional interconnects with high aspect ratio TSVs and fine pitch solder microbumps. In: IEEE proceedings of ECTC, San Diego, CA; May 2009. p. 350-4. IEEE transactions in advanced packaging, in press.
-
(2009)
IEEE Proceedings of ECTC
, pp. 350-354
-
-
Yu, A.1
Lau, J.H.2
Ho, S.3
Kumar, A.4
Yin, H.5
Ching, J.6
-
18
-
-
63049114343
-
Development of fine pitch solder microbumps for 3D chip stacking
-
December IEEE transactions in advanced packaging, in press
-
Yu A, Kumar A, Ho S, Yin H, Lau JH, Ching J, et al. Development of fine pitch solder microbumps for 3D chip stacking. In: IEEE EPTC proceedings, Singapore; December 2008. p. 387-92. IEEE transactions in advanced packaging, in press.
-
(2008)
IEEE EPTC Proceedings, Singapore
, pp. 387-392
-
-
Yu, A.1
Kumar, A.2
Ho, S.3
Yin, H.4
Lau, J.H.5
Ching, J.6
-
19
-
-
70349299917
-
Development of silicon carriers with embedded thermal solutions for high power 3-D package
-
A. Yu, N. Khan, G. Archit, D. Pinjalal, K. Toh, and V. Kripesh Development of silicon carriers with embedded thermal solutions for high power 3-D package IEEE Trans Comp Pack Technol 32 3 2009 566 571
-
(2009)
IEEE Trans Comp Pack Technol
, vol.32
, Issue.3
, pp. 566-571
-
-
Yu, A.1
Khan, N.2
Archit, G.3
Pinjalal, D.4
Toh, K.5
Kripesh, V.6
-
20
-
-
77949562449
-
Integrated liquid cooling systems for 3-D stacked TSV modules
-
G. Tang, O. Navas, D. Pinjala, J.H. Lau, A. Yu, and V. Kripesh Integrated liquid cooling systems for 3-D stacked TSV modules IEEE Trans Comp Pack Technol 33 1 2010 184 195
-
(2010)
IEEE Trans Comp Pack Technol
, vol.33
, Issue.1
, pp. 184-195
-
-
Tang, G.1
Navas, O.2
Pinjala, D.3
Lau, J.H.4
Yu, A.5
Kripesh, V.6
-
21
-
-
70349658299
-
Development of through silicon via (TSV) interposer technology for large die (21×21mm) fine-pitch Cu/low-k FCBGA package
-
May IEEE transactions in advanced packaging, in press
-
Zhang X, Chai T, Lau JH, Selvanayagam C, Biswas K, Liu S, et al. Development of through silicon via (TSV) interposer technology for large die (21×21mm) fine-pitch Cu/low-k FCBGA package. In: IEEE proceedings of ECTC; May, 2009. p. 305-12. IEEE transactions in advanced packaging, in press.
-
(2009)
IEEE Proceedings of ECTC
, pp. 305-312
-
-
Zhang, X.1
Chai, T.2
Lau, J.H.3
Selvanayagam, C.4
Biswas, K.5
Liu, S.6
-
22
-
-
79951937106
-
Evaluation of stresses in thin device wafer using piezoresistive stress sensor
-
December IEEE transactions in components and packaging technologies, in press
-
Kumar A, Zhang X, Zhang Q, Jong M, Huang G, Kripesh V, et al. Evaluation of stresses in thin device wafer using piezoresistive stress sensor. In: IEEE proceedings of EPTC; December 2008. p. 1270-6. IEEE transactions in components and packaging technologies, in press.
-
(2008)
IEEE Proceedings of EPTC
, pp. 1270-1276
-
-
Kumar, A.1
Zhang, X.2
Zhang, Q.3
Jong, M.4
Huang, G.5
Kripesh, V.6
-
23
-
-
70349670743
-
Development of 3-D silicon die stacked package using flip chip technology with micro bump interconnects
-
San Diego, CA; May IEEE transactions in CPMT, in press
-
Vempati1 SR, Nandar S, Khong C, Lim Y, Vaidyanathan K, Lau JH, et al. Development of 3-D silicon die stacked package using flip chip technology with micro bump interconnects. In: IEEE proceedings of ECTC San Diego, CA; May, 2009. p. 980-7. IEEE transactions in CPMT, in press.
-
(2009)
IEEE Proceedings of ECTC
, pp. 980-987
-
-
Vempati, S.R.1
Nandar, S.2
Khong, C.3
Lim, Y.4
Vaidyanathan, K.5
Lau, J.H.6
-
24
-
-
63049096701
-
Process development and reliability of microbumps
-
December IEEE transactions in components and packaging technology, in press
-
Lim S, Rao V, Yin H, Ching W, Kripesh V, Lee C, et al. Process development and reliability of microbumps. In: IEEE proceedings of electronic packaging technology conference; December 2008. p. 367-72. IEEE transactions in components and packaging technology, in press.
-
(2008)
IEEE Proceedings of Electronic Packaging Technology Conference
, pp. 367-372
-
-
Lim, S.1
Rao, V.2
Yin, H.3
Ching, W.4
Kripesh, V.5
Lee, C.6
-
25
-
-
74649084751
-
Nonlinear thermal stress/strain analysis of copper filled TSV (Through Silicon Via) and their flip-chip microbumps
-
C. Selvanayagam, J.H. Lau, X. Zhang, S. Seah, K. Vaidyanathan, and T. Chai Nonlinear thermal stress/strain analysis of copper filled TSV (Through Silicon Via) and their flip-chip microbumps IEEE Trans Adv Pack 32 4 2009 720 728
-
(2009)
IEEE Trans Adv Pack
, vol.32
, Issue.4
, pp. 720-728
-
-
Selvanayagam, C.1
Lau, J.H.2
Zhang, X.3
Seah, S.4
Vaidyanathan, K.5
Chai, T.6
-
26
-
-
58349104327
-
Study of low temperature thermocompression bonding in Ag-In solder for packaging applications
-
R. Made, C.L. Gan, L. Yan, A. Yu, S.U. Yoon, and J.H. Lau Study of low temperature thermocompression bonding in Ag-In solder for packaging applications J Electron Mater 38 2009 365 371
-
(2009)
J Electron Mater
, vol.38
, pp. 365-371
-
-
Made, R.1
Gan, C.L.2
Yan, L.3
Yu, A.4
Yoon, S.U.5
Lau, J.H.6
-
27
-
-
57649222007
-
A hermetic seal using composite thin solder In/Sn as intermediate layer and its interdiffusion reaction with Cu
-
L.-L. Yan, C.-K. Lee, D.-Q. Yu, A.-B. Yu, W.-K. Choi, and J.H. Lau A hermetic seal using composite thin solder In/Sn as intermediate layer and its interdiffusion reaction with Cu J Electron Mater 38 2009 200 207
-
(2009)
J Electron Mater
, vol.38
, pp. 200-207
-
-
Yan, L.-L.1
Lee, C.-K.2
Yu, D.-Q.3
Yu, A.-B.4
Choi, W.-K.5
Lau, J.H.6
-
28
-
-
84867571667
-
Characterization of intermediate In/Ag layers of low temperature fluxless solder based wafer bonding for MEMS packaging
-
in press
-
Lee C, Yu A, Yan L, Wang H, Han J, Zhang Q, et al. Characterization of intermediate In/Ag layers of low temperature fluxless solder based wafer bonding for MEMS packaging. J Sens Actuators, in press.
-
J Sens Actuators
-
-
Lee, C.1
Yu, A.2
Yan, L.3
Wang, H.4
Han, J.5
Zhang, Q.6
-
29
-
-
58849125006
-
The role of Ni buffer layer on high yield low temperature hermetic wafer bonding using In/Sn/Cu metallization
-
D.-Q. Yu, C. Lee, L.L. Yan, W.K. Choi, A. Yu, and J.H. Lau The role of Ni buffer layer on high yield low temperature hermetic wafer bonding using In/Sn/Cu metallization Appl Phys Lett 94 3 2009 34105 34105-3
-
(2009)
Appl Phys Lett
, vol.94
, Issue.3
, pp. 34105-341053
-
-
Yu, D.-Q.1
Lee, C.2
Yan, L.L.3
Choi, W.K.4
Yu, A.5
Lau, J.H.6
-
30
-
-
71649088048
-
Application of piezoresistive stress sensors in ultra thin device handling and characterization
-
X. Zhang, A. Kumar, Q.X. Zhang, Y.Y. Ong, S.W. Ho, and C.H. Khong Application of piezoresistive stress sensors in ultra thin device handling and characterization J Sens Actuators: A Phys 156 2009 2 7
-
(2009)
J Sens Actuators: A Phys
, vol.156
, pp. 2-7
-
-
Zhang, X.1
Kumar, A.2
Zhang, Q.X.3
Ong, Y.Y.4
Ho, S.W.5
Khong, C.H.6
-
34
-
-
32844465150
-
Simple formulas for estimating thermal spreading resistance
-
R.E. Simons Simple formulas for estimating thermal spreading resistance Electron Cool 10 2004 6 8
-
(2004)
Electron Cool
, vol.10
, pp. 6-8
-
-
Simons, R.E.1
|