Oxide liner, barrier and seed layers, and Cu plating of blind through silicon vias (TSVs) on 300 mm wafers for 3D IC integration

Journal of Microelectronics and Electronic Packaging

Volumn 9, Issue 1, 2012, Pages 31-36

  Wu, Chien Ying ^a   Chen, Shang Chun ^a   Tzeng, Pei Jer ^a   Lau, John H ^a   Hsu, Yi Feng ^a   Chen, Jui Chin ^a   Hsin, Yu Chen ^a   Chen, Chien Chou ^a   Shen, Shang Hung ^a   Lin, Cha Hsin ^a   Ku, Tzu Kun ^a   Kao, Ming Jer ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

3D IC integration; Barrier and seed layers; Cu plating; Leakage current; Oxide liner; Through silicon via (TSV)

Indexed keywords

COPPER PLATING; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT INTERCONNECTS; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATION; LEAKAGE CURRENTS; SILICON WAFERS; TIMING CIRCUITS;

3-D INTEGRATION; 300 MM WAFERS; CU PLATINGS; ENABLING TECHNOLOGIES; OXIDE LINERS; SEED LAYER; THROUGH SILICON VIAS; THROUGH-SILICON-VIA (TSV);

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 84880297800     PISSN: 15514897     EISSN: None     Source Type: Journal    
DOI: 10.4071/imaps.308     Document Type: Article

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