3-D packaging with through-silicon via (TSV) for electrical and fluidic interconnections

IEEE Transactions on Components, Packaging and Manufacturing Technology

Volumn 3, Issue 2, 2013, Pages 221-228

  Khan, Navas ^a,b   Yu, Li Hong ^a   Pin, Tan Siow ^c   Ho, Soon Wee ^a   Kripesh, Vaidyanathan ^a   Pinjala, Damaruganath ^a   Lau, John H ^a,d   Chuan, Toh Kok ^c  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b FREESCALE SEMICONDUCTOR INC   (United States)

^c NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^d INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

3 D packaging; liquid cooling; micro channel cooling

Indexed keywords

3-D PACKAGES; 3D PACKAGING; CHIP CARRIER; COOLING LIQUID; ELECTRICAL INTERCONNECTIONS; FLUIDIC CHANNELS; FLUIDIC INTERCONNECTIONS; HEAT TRANSFER ENHANCEMENT; HERMETIC SEALING; LIQUID COOLING; SEALING TECHNIQUE; SILICON CARRIERS; TWO-STACK;

CHIP SCALE PACKAGES; COOLING;

LIQUIDS;

EID: 84873458121     PISSN: 21563950     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCPMT.2012.2186297     Document Type: Article

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