Advanced low profile PoP solution with embedded wafer level PoP (eWLB-PoP) technology

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2012, Pages 1250-1254

  Yoon, Seung Wook ^a   Caparas, Jose Alvin ^a   Lin, Yaojian ^a   Marimuthu, Pandi C ^a  

^a STATS CHIPPAC LTD   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

3D PACKAGING; 3D TECHNOLOGY; APPLICATION PROCESSORS; ASSEMBLY PROCESS; BOARD-LEVEL RELIABILITY; BUILDING BLOCKES; COMPONENT PACKAGING; DEVICE DESIGN; ENABLING TECHNOLOGIES; FORM FACTORS; FUNCTIONAL INTEGRATION; INTERCONNECTION DENSITY; MECHANICAL CHARACTERIZATIONS; MOBILE APPLICATIONS; NEW TECHNOLOGY DEVELOPMENT; PACKAGE CONFIGURATIONS; PACKAGE RELIABILITY; PACKAGE SIZE; PACKAGE STRUCTURE; PORTABLE ELECTRONICS; RELIABILITY CHARACTERIZATION; SIGNAL ROUTING; SYSTEM LEVEL INTEGRATION; TEST VEHICLE; TOP SURFACE; WAFER LEVEL;

APPROXIMATION THEORY; ELECTRONIC EQUIPMENT; ELECTRONICS PACKAGING; RELIABILITY; TECHNOLOGY; THREE DIMENSIONAL COMPUTER GRAPHICS;

PACKAGING;

EID: 84866839778     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2012.6248995     Document Type: Conference Paper

References (4)

1. M. Brunnbauer, et al., "Embedded Wafer Level Ball Grid Array (eWLB)," Proceedings of 8th Electronic Packaging Technology Conference, 10-12 Dec 2009, Singapore (2006)
2. Graham pitcher, "Good things in small packages," Newelectronics, 23 June 2009, p18-19 ( 2009)
3. Seung Wook YOON, Meenakshi PADMANATHAN, Andreas BAHR, Xavier BARATON and Flynn CARSON, "3D eWLB (embedded wafer level BGA) Technology: Next Generation 3D Packaging solutions," San Francisco, IWLPC 2009 (2009)
4. Hnmid Eslampour. Seong Min Lee. Seong Won Park. Tae Keun Lee, In Sang Yoon, Voung ChuI Kim, "Comparison of Advanced PoP Package Configurations. Proce", Proceedings of ECTC 2010, Rino, US (2010)