Nanometer CMOS ICs: From Basics to ASICs

Nanometer CMOS ICs: From Basics to ASICs

Volumn , Issue , 2017, Pages 1-611

  Veendrick, Harry J M ^a  

^a NONE   (Netherlands)

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[No Author keywords available]

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EID: 85055067624     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1007/978-3-319-47597-4     Document Type: Book

References (349)

1. ITRS Roadmap (2014), www. ITRS.net For Further Reading General Basic Physics
2. R.S.C. Cobbold, Theory and Applications of Field Effect Transistors (Wiley, New York, 1970)
3. S.M. Sze, Semiconductor Devices: Physics and Technology, 2nd edn. (Illustrated) (Wiley, New York, 2001)
4. Y.P. Tsividis, Operation and Modelling of the MOS Transistor (WCB Mc Graw-Hill, Boston 1999)
5. C. Kittel, Introduction to Solid State Physics 7th edn. (Wiley, New York, 1996)
6. D. Bhattacharya, N.K. Jha, FinFETs: from devices to architectures. Adv. Electron. 2014, Article ID 365689, 21 p (2014). http://www.hindawi.com/archive/2014/365689/
7. B. Ho, Evolutionary MOSFET Structure and Channel Design for Nanoscale CMOS Technology, Dissertation for University of California, Berkeley, Fall 2012 MOS Capacitances
8. E.W. Greenwich, An analytical model for the gate capacity of small-geometryMOS structures. IEEE Trans. Electron Dev. 30, 1838-1839 (1983)
9. J.J. Paulos, D.A. Antoniadis, Y.P. Tsividis, Measurement of intrinsic capacitances of MOS transistors. ISSCC Digest of Technical Papers, pp. 238-239 (1982)
10. D.E. Ward, R.W. Dutton, A charge-oriented model for MOS transistor capacitances. IEEE J. Solid-State Circuits sc-13, 703-707 (1978)
11. H. Kogure et al., Analysis of CMOS ADC non-linear input capacitance. IEICE Trans. Electron. E85-C(5), 1182-1190, (2002)
12. Chenming-Hu, MOS Capacitor, Chapter 5, Friday, February 13, 2009, p. 194
13. A.J. Walker, P.H. Woerlee, A mobility model for MOSFET device simulations. J. Phys. colloque C4 49(9), 256 1988
14. M. Vertregt, The Analog Challenge in Nanometer CMOS. IEDM Digest of Technical Papers, pp. 11-18 (2006)
15. N. Weste, D.M. Harris, CMOS VLSI Design, A Systems Perspective, 4th edn. (Addison-Wesley, Boston, 2011)
16. R.S.C. Cobbold, Theory and Applications of Field Effect Transistors (Wiley, New York, 1970)
17. I.M. Filanovsky, A. Allam, Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits. IEEE Trans. Circuits Syst. Fundam. Theory Appl. 48(7), 876-884 (2001)
18. E. Long et al., Detection of temperature sensitive defects using ZTC, in Proceedings of 22nd IEEE VLSI Test Symposium (VTS 2004)
19. A. Dasnan et al., Handling inverted temperature dependance in static timing analysis. ACM Trans. Design Autom. Electronic Syst. 11(2), 306-324 (2006)
20. R. Kumar et al., Reversed temperature-dependent propagation delay characteristics in nanometer CMOS circuits. IEEE Trans. Circuits Syst. II: Express Briefs 53(10), 1078-1082 (2006)
21. R. van Langevelde et al., Gate current: modelling, ΔL extraction and impact on RF performance. IEDM Technical Digest, pp. 289-292 (2001)
22. F. Hamzaoglu et al., Circuit-level techniques to control gate leakage for sub-100nm CMOS, in Proceedings of the 2002 ISLPED Symposium, pp. 60-63
23. G. Gildenblat et al., PSP: an advanced surface-potential-based MOSFET model for circuit simulation. IEEE Trans. Electron Dev. 53(9), 1979-1993 (2006)
24. D. Lee et al., Gate Oxide leakage current analysis and reduction for VLSI circuits. IEEE Trans. VLSI Syst. 12(2), 155-166 (2004)
25. J. Assenmacher, BSIM4 modelling and Parameter Extraction (2003). http://www.ieee.org/r5/denver/sscs/References/2003_03_Assenmacher.pdf
26. G. Marcyk et al., New Transistors for 2005 and Beyond, http://www.eas.asu.edu/~vasilesk/EEE531/TeraHertzlong.pdf
27. A. Scholten et al., The physical background of JUNCAP2. IEEE Trans. Electron Dev. 53(9), 2098-2107 (2006)
28. R. Woltjer et al., An industrial view on compact modeling, in Proceedings of the 36th European Solid-State Device Research Conference, Sept 2006, pp. 41-48 General Basic Physics
29. S.M. Sze, Very Large Scale Integration Technology, 2nd edn. (Mc Graw-Hill, New York, 1998)
30. M. LaPedus et al., What Happened to 450mm? Semiconductor Engineering, July 17, 2014
31. IC Insights, CompaniesMaximize 300mm, 200mmWafers; Slow Progress on 450mm', Design & reuse, Sept. 14, 2015, http://www.design-reuse.com/news/38229/global-wafer-capacity- 2015-2019-report.html
32. R. Wilson, Chip industry tackles escalating mask costs. EE Times, 6/17/2002
33. M. Porrini, Growing Ingots of Single Crystal Si, in MEMC SiliconWorkshop at IMEC, Leuven, Belgium, June 22, 2006
34. G. Vaccari, Silicon Epitaxi for CMOS and Power Applications, in MEMC Silicon Workshop at IMEC, Leueven, Belgium, June 22, 2006
35. L. Chang et al., CMOS circuit performance enhancement by surface orietation optimization. pp. 1621-1627, IEEE Trans. Electron Dev. 51(10), 1621-1627 (2004)
36. M. Yang et al., Hybrid-orientation technology (HOT): opportunities and challenges. pp. 965-978, IEEE Trans. Electron Dev. 53(5), 965-978 (2006)
37. S. Reddy Alla, Ultra thin body SOI FETs, http://www.slideshare.net/sindhureddy14/538-34932218, May 20, 2014
38. T. Buchholtz et al., A 660 MHz 64b SOI processor with Cu interconnects. ISSCC, Digest of Technical Papers, Feb 2000
39. J.L. Pelloie et al., SOI technology performance and modelling. ISSCC, Digest of Technical Papers (1999), pp. 428-429
40. H. Majima et al., Experimental evidence for quantum mechanical narrow channel effect. IEEE Electron Dev. Lett. 21, 396-398 (2000)
41. T. Lecklider, Yield: The Key to Nanometer Profits. Evaluation Engineering, Mar 2005 www. evaluationengineering.com/archive/articles/0305/0305yield.asp
42. Y.K. Choi et al., Sublithographic nanofabrication technology for nanocatalysts and DNA chips. J. Vac. Sci. Technol. B21(6), 2951-2955 (2003)
43. M. David Levenson, Advanced Lithography is All about Materials (2011). http://www. betasights.net/wordpress/?p=1273
44. J. Kwan, Sign-offlithography simulation and multi-patterning must play well together, http://www.techdesignforums.com/practice/tag/multi-patterning/Aug 12, 2014
45. Y.-K. Choi, Multiple Gate CMOS and Beyond Nanotechnology-forum, Forum_6, Seoel, June 5-6, 2012
46. D.C. Brandt et al., Laser Produced Plasma EUV Sources for Device Development and HVM (2012). http://www.cymer.com/files/pdfs/Technology/2012/Laser_Produced_Plasma_ EUV_Sources_for_Device:Development_and_HVM.pdf
47. M. LaPedus, ASML ships world's first EUV tool, www.eetimes.com, Aug 28, 2006
48. M. Feldman (ed.), Nanolithography: The Art of Fabricating Nanoelectronic and Nanophotonic Devices and Systems. Woodhead Publishing Series in Electronic and Optical Materials (Woodhead Publishing, Oxford, 2014)
49. H. Mizoguchi et al., Performance of 100-W HVM LPP-EUV source. Adv. Opt. Technol. 4(4), 297-309 (2015)
50. I. Fomenkov, Status and outlook of LPP light sources for HVM EUV, in EUVL Workshop 2015, June 18th, 2015
51. P. Clarke, Report: Toshiba adopts imprint litho for NAND production, EE Times (Analog), June 07, 2016
52. G. de Boer et al., MAPPER: progress toward a high-volume manufacturing system. SPIE Proceedings, vol. 8680: Alternative Lithographic Technologies V, Mar 2013
53. Ed Korczynski, EUV Resists and Stochastic Processes, Semiconductor Manufacturing & Design Community http://semimd.com/blog/tag/euv/Mar 4, 2016
54. P. Singer, Nanoimprint Lithography: A Contender for 32 nm?' Semiconductor International, Issue Aug 1, 2006
55. K. Jeong et al., New yield-aware mask strategies, in Proceedings of SPIE, vol. 8081, 80810P (SPIE, 2011)
56. H.C. Pfeiffer et al., Microlithography World - the history and potential of maskless Ebeam lithography, Solid State Technology, Feb 2005, http://sst.pennnet.com/Articles/Article_ Display.cfm?Section=ARTCL&ARTICLE_ID=221612&VERSION_NUM=4&p=28
57. K. Suzuki, N. Itabashi, Future prospects for dry etching. Pure Appl. Chem. 68(5), 1011-1015 (1996)
58. G. Lee, Flash below 20 nm: What is coming and when. Challenges in 3-D NAND, Flash Memory Summit 2013
59. D. Pramanik, Challenges for intermetal dielectrics, Future Fab International (1997)
60. Process Integration, Devices, and Structures (PIDS), Tables, ITRS Roadmap, edition 2011
61. D.-G. Park, X. Wang, High-k gate dielectrics for nanoscale CMOS devices: status, challenges. ECS Trans. 28(2), 39-50, The Electrical Chemical Society (2010)
62. T. Faraz et al., Atomic layer etching: what can we learn from atomic layer deposition? ECS J. Solid State Sci. Technol. 4(6), N5023-N5032 (2015)
63. B. Mann, Development of thin gate oxides for advanced CMOS applications, in 22nd Annual Microelectronic Engineering Conference, May 2004
64. Y. Mitani et al., NBTI Mechanism in ultra-thin gate dielectric-nitrogen-originated mechanism in SiON-, International Electron Devices Meeting Technical Digest, pp. 509-512 (2002)
65. S. Wolf, R.N. Tauber, Silicon Processing for the VLSI Era, vol. 1: Process Technology (Lattice Press, Sunset Beach, 1986)
66. J. Hruska, How combining cobalt and copper could improve chip yields, boost performance. ExtremeTech, May 14, 2014, http://www.extremetech.com/extreme/182386-how-combiningcobalt- and-copper-could-improve-chip-yields-boost-performance
67. S.-H. Yu et al., Selective cobalt deposition on copper surfaces, US Patent 20090269507 A1, Oct 29, 2008
68. B.S. Lim et al., Atomic layer deposition of transition metals. Nature Materials, vol. 2, Nov 2003, www.nature.com/naturematerials
69. L. Rubin, J. Poate, Ion Implantation in Silicon Technology. The Industrial Physicist, June/July 2003, pp. 12-15
70. R.F.M. Roes et al., Implications of pocket optimisation on analog performance in deep submicron CMOS. ESSDERC, Digest of Technical Papers, pp. 176-179 (1999)
71. M. Bohr et al., The High-k Solution. IEEE Spectrum, Oct 2007, pp. 23-29
72. Y. Song, Source/drain technologies for the scaling of nanoscale CMOS device. Solid-State Sci. 13, 294-305 (2013)
73. S. Kesapragada et al., High-k/metal gate stacks in gate first and replacement gate schemes, Advanced Semiconductor Manufacturing Conference (ASMC) (IEEE/SEMI, 2010), pp. 256-259
74. Gate-last and gate-first high-k metal, IMEC Scientific Report 2010, http://www.imec.be/ScientificReport/SR2010/2010/1159059.html
75. B. Moyer, Gate First vs. Last. Electronic Engineering Journal, Posted on Nov 14, 2011, http://www.eejournal.com/archives/articles/20111114-gate/
76. S. Thompson et al., A 90nm logic technology featuring 50nm strained silicon channel transistors, 7 layers of Cu interconnects, low-k ILD, and 1 mm SRAM cell', in IEEE International Electron Devices Meeting (2002)
77. G. Eneman et al., N+/P and P+/N Junctions in Strained Si on Strain Relaxed SiGe Buffers: the Effect of Defect Density and Layer Structure. Mater. Res. Soc. Symp. Proc., vol. 864. © 2005 Materials Research Society, pp. E3.7.1-E3.7.6
78. P.R. Chidambaram, 35% drive current improvement from recessed-SiGe drain extensions on 37 nm gate length PMOS, in 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 48-49
79. M. Yang et al., High Performance CMOS Fabricated on Hybrid Substrate With Different Crystal Orientations Electron Devices Meeting. IEDM '03 Technical Digest (2003)
80. M.-H. Chi, Challenges inManufacturing FinFET at 20 nmnode and beyond (2012). http://www. rit.edu/kgcoe/eme/sites/default/files/Min-hwa%20Chi%20-%20abstract_%20Challenges %20in%20Manufacturing%20FinFET.pdf
81. T. Dillinger, Challenges for FinFET Extraction, in IEEE Electronic Design Process Symposium, Apr 15, 2013
82. D.R. Muralidher et al., Meeting the challenge of multiple threshold voltages in highly scaled undoped FinFETs. IEEE Trans. Electron Dev. 60(3), 1276-1278 (2013)
83. X. Wang et al., Statistical variability and reliability in nanoscale FinFETs, in Proceedings of the IEEE International Electron Devices Meeting (IEDM '11), Washington, DC, Dec 2011, pp. 541-544
84. S. Chaudhuri, N.K. Jha, 3D vs. 2D analysis of FinFET logic gates under process variations, in Proceedings of the 29th IEEE International Conference on Computer Design (ICCD '11), Amherst, MA, Nov 2011, pp. 435-436
85. P. Clarke, Intel's FinFETs are less fin and more triangle, May 17, 2012, http://www.embedded. com/electronics-news/4373195/Intel-FinFETs-shape-revealed
86. J.-H. Lee, Bulk FinFETs: design at 14 nm node and key characteristics, in Nano Devices and Circuit Techniques for Low-Energy Applications and Energy Harvesting, ed. by C.M. Kyung (Springer, Dordrecht, 2016), pp. 33-64. ISBN:978-94-017-9989-8
87. LexInnova Technologies LLC, 'FinFET' Extending Moore's law', Report (2015), http://www.wipo.int/export/sites/www/patentscope/en/programs/patent_landscapes/documents/lexinnova_plr_finfet.pdf
88. Rieger et al., Self-aligned via interconnect using relaxed patterning exposure. US 2014/0015135 A1, Jan. 16, 2014
89. D. Fried et al., Comparison study of FinFETs: SOI vs. bulk, performance, manufacturing variability and cost' SOI industry consortium (2011). http://www.soiconsortium.org/pdf/Comparison%20study%20of%20FinFETs%20-%20SOI%20versus%20Bulk.pdf
90. M. Haond, FDSOI for Low Power System on chip (2011). http://semieurope.omnibooksonline. com/2011/semicon_europa/SEMI_TechARENA_presentations/NewMaterial_05_Michel. Haond_STMicroelectronics.pdf
91. A. Majumdar, Undoped-body extremely thin SOI MOSFETs with back gates. IEEE Trans. Electron Dev. 56(10), 2270-2276 (2009)
92. B. Prince, Vertical 3-D Memory Technologies. ISBN: 978-1-118-76051-2 (Wiley, New York, 2014)
93. X. Kang et al., Cu/Airgap integration on 90nm Cu BEOL process platform, in 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT)
94. D. James, IEDM 2014 Monday was FinFET Day, Dec 18, 2014, https://www.chipworks.com/about-chipworks/overview/blog/iedm-%E2%80%93-monday-was-finfet-day
95. W. Steinhogl et al., Size-dependent resistivity of metallic wires in mesoscopic range. Phys. Rev. B 66, 075414 (2002)
96. P. Kapur et al., Technology and reliability constrained future copper interconnects - part I: resistance modelling. IEEE Trans. Electron Dev. 49(4), 590-597 (2002)
97. C. Mead, L. Conway, Introduction to VLSI Systems (Addison-Wesley, Reading, MA, 1980)
98. L.G. Heller et al., Cascode Voltage Switch Logic. IEEE Digest of Technical Papers of the ISSCC (1984)
99. International Solid-State Circuits Conference Digest of Technical papers, Feb 2000, pp. 90-11, 176-177, 412-413, 422-423
100. S. Rusu, IEEE Distinguished Lecture. Microprocessor Design in the Nanoscale Era. IEEE Penang Joint Chapter, July 29, 2013
101. T. Cui et al., 7nm FinFET standard cell layout characterization and power density prediction in near- and super-threshold voltage regimes, in 2014 International Green Computing Conference (IGCC), 3-5 Nov 2014
102. P. McLellan, FinFET Custom Design. SemiWiki.com, The open Forum for Semiconductor Professionals, 04-02-2014
103. K. Vaidyanathan et al., Exploiting sub-20-nm complementary metal-oxide semiconductor technology challenges to design affordable systems-on-chip. J. Micro/Nanolith. MEMS MOEMS. 14(1), 011007 (2014) Power Dissipation in CMOS
104. H.J.M. Veendrick, Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits. IEEE J. Solid State Circuits SC-19(4), 468-473 (1984)
105. IEEE Journal of Solid-State Circuits
106. ISSCC and ESSCIRC Conferences, VLSI and ISLPED Symposia, Digests of Technical Papers
107. R.C. Jaeger, Introduction to Microelectronic Fabrication. Modular Series on Solid-State Devices, vol. 5, (Addison-Wesley, Reading, MA, 1988)
108. Y. Sakai et al., Advanced Hi-Cmos device technology. IEEE IEDM, Washington DC, pp. 534-537 (1981)
109. S.M. Sze, Modern Semiconductor Device Physics (Wiley, New York, 1997)
110. S. Wolf, R.N. Tauber, Silicon Processing for the VLSI Era, vol. 1, Process Technology (Lattice Press, Sunset Beach, CA, 1986)
111. N. Weste, K. Eshraghian, Principles of CMOS VLSI Design, A Systems Perspective (Addison- Wesley, Reading, MA, 1993)
112. L.A. Glasser, D.W. Dobberpuhl, The Design and Analysis of VLSI Circuits (Addison-Wesley, Reading, MA, 1985)
113. M. Annaratone, Digital CMOS Circuit Design (Kluwer Academic Publishers, Boston, 1986)
114. J.M. Rabaey, Digital Integrated Circuits: A Design Perspective (Prentice Hall, Englewood Cliffs, 1995)
115. K. Bernstein et al., High Speed CMOS Design Styles (Kluwer Academic Publishers, Boston, 1999)
116. Image Sensor Session at the ISSCC Conferences: ISSCC Digest of Technical Papers, 2000-2016
117. E.R. Fossum, CMOS image sensors: electronic camera-on-a-chip. IEEE Trans. Electron Dev. 44, 1689-1698 (1997)
118. K.-B. Cho et al., A 1/2.5 inch 8.1 Mpixel CMOS Image Sensor for Digital Cameras. ISSCC Digest of Technical Papers, pp. 508-509 (2007)
119. A.J.P. Theuwissen, Better pictures through physics: the state of the art of CMOS image sensors. IEEE Solid-State Circuits Mag. 22-28, Spring (2010)
120. R. Lerner et al., Comparison of different device concepts to increase the operating voltage of a trench isolated SOI technology to above 900V. Facta Univ. Ser. Electron. Energetics 28(4), 645-656 (2015)
121. F. Udrea et al., SOI-based devices and technologies for high voltage ICs. BCTM, pp. 74-79 (2007)
122. H. Gensinger, High-Voltage CMOS Technologies for Robust System-on-Chip Design. HVCMOS_ FSA Forum, June 2006
123. A. Ludikhuize, A versatile 250/300V IC process for analog and switching applications. IEEE Trans. Electron Dev. ED-33, 2008-2015 (1986)
124. P. Blanken, P. van der Zee, An integrated 8MHz video output amplifier. IEEE Trans. Consum. Electron. CE-31, 109 (1985)
125. P. Blanken, J. Verdaasdonk, An integrated 150Vpp, 12kV/s class AB CRT-driving amplifier. ISSCC, Digest of Technical Papers, New York (1989)
126. K. Washio et al., SiGe HBT and BiCMOS Technologies. IEDM, Digest of Technical Papers, Session 5.1.3 (2003)
127. J. Donkers et al., Vertical Profile Optimisation of a Self-Aligned SiGeC HBT Process with an n-Cap Emitter. IEEE/BCTM (2003)
128. J. Donkers et al., Metal Emitter SiGe:C HBTs. IEDM, Digest of Technical Papers (2004)
129. L.J. Choi et al., A Novel Isolation Scheme featuring Cavities in the Collector for a High-Speed 0.13 m SiGe:C BiCMOS Technology, SiRF, 2007
130. M. Khater et al., SiGe HBT technology with fmax=fT D 350=300 GHz and gate delay below 3.3 ps. IEDM, Digest of Technical Papers, pp. 247-250 (2004)
131. P. Deixler et al., QUBiC4plus: a cost-effective BiCMOS manufacturing technology with elite passive enhancements optimized for 'silicon-based' RF-system-in-package environment. Bipolar/BiCMOS Circuits and Technology Meeting, pp. 272-275 (2005)
132. Y. Ruan et al., A monolithic SiGe BiCMOS power amplifier for UHF RFID application, in 11th International Conference on Wireless Communications, Networking and Mobile Computing (WiCOM 2015) (2015), p. 3
133. E. öztürk et al., An ultra-wideband SiGe BiCMOS LNA for W-band applications. Microw. Opt. Technol. Lett. 57(6), 1274-1278 (2015)
134. V. Valenta et al., SiGe: C BiCMOS components and integrated solutions for F-band radar frontends (2015), https://hal.archives-ouvertes.fr/hal-01131093/document
135. H. Boezen, SOI in Automotive IC Design. SOI Workshop, July 2015, http://www. soiconsortium.org/fully-depleted-soi/presentations/silicon-saxony-day-2015/3.%20SOI %20Workshop%20SOI%20in%20Automotive%20IC%20Design%20Henk%20Boezen.pdf
136. K. Pagiamtzis et al., Content-addressable memory (CAM) circuits and architectures: a tutorial and survey. IEEE J. Solid-State Circuits 41(3), 712-727 (2006)
137. K. Noda et al., A 1.9 m2 Loadless CMOS Four Transistor SRAM Cell in a 0.18 m Logic Technology. IEDM Digest of Technical Papers, Dec 1998, pp. 643-646
138. K. Takeda et al., A 16Mb 400MHz loadless CMOS 4-Transistor SRAMMacro. ISSCC Digest of Technical Papers, Feb 2000
139. L. Chang et al., Stable SRAM Cell Design for the 32 nm Node and Beyond, in 2005 Symposium on VLSI Technology, Digest of Technical Papers, pp. 128-129
140. S.M. Jung et al., Highly Area Efficient and Cost Effective Double Stacked S (Stacked Singlecrystal Si) peripheral CMOS SSTFT and SRAM Cell Technology for 512Mb SRAM. IEDM 2004, Digest of Technical Papers, pp. 265-268
141. J. Keane et al., 5.6Mb/mm2 1R1W 8T SRAM Arrays Operating down to 560mV Utilizing Small-Signal Sensing with Charge-Shared Bitline and Asymmetric Sense Amplifier in 14nm FinFET CMOS Technology Charge-Shared Bitline and Asymmetric Sense Amplifier in 14nm FinFET CMOS Technology. ISSCC 2016, Digest of Technical Papers, Feb 2016, pp. 308-309
142. A Reconfigurable Dual-Port Memory with Error Detection and Correction in 28nm FDSOI. ISSCC 2016, Digest of Technical Papers, Feb 2016, pp. 310-311
143. E. Karl et al., The impact of assist-circuit design for 22 nm SRAM and beyond. IEDM Technical Digest, pp. 561-564 (2012)
144. T. Song et al., A 10nm FinFET 128Mb SRAM with Assist Adjustment System for Power, Performance and Area Optimization. ISSCC 2016, Digest of Technical Papers, Feb 2016, pp. 306-307
145. J. Wan et al., Z2-FET used as 1-Transistor High-Speed DRAM. ESSDERC, Digest of Technical Papers (2012)
146. Designing for 1GB DDR SDRAM. Micron Technology, Technical Note, 2003
147. C. Cho et al., A 6F2 DRAM Technology in 60 nm era for Gigabit Densities, in 2005 Symposium on VLSI Technology, Digest of Technical Papers, pp. 36-37
148. J.A. Mandelman et al., Challenges for future directions for the scaling of DRAM. IBM J. Res. Dev. 46(2/3), 187-212 (2002)
149. H. Seidl et al., A fully integrated Al2O3 trench capacitor DRAM for sub-100 nm technology. IEDM, 2002
150. C. Hampel, High-speed DRAMs keep pace with high-speed systems. EDN, Feb 3, 1997, pp. 141-148
151. C. Green, Analyzing and implementing SDRAM and SGRAM controllers. EDN, Feb 2, 1998, pp. 155-166
152. R. Faramarzi, High Speed Trends In Memory Market. Keynote address, Jedex Conference, Oct 25-26, 2006, Shanghai, http://www.jedexchina.org/program.htm
153. T. Schmitz, The Rise of Serial Memory and the Future of DDR, Xilinx, WP456 (v1.1) Mar 23, 2015
154. Samsung Develops Ultra-fast Graphics Memory: A More Advanced GDDR4 at Higher Density, Press Release (Feb 14, 2006/SEC)
155. Understanding Video (VRAM) and SGRAM operation (1996). http://www.chips.ibm.com/products/memory
156. D. Bursky, Graphics-Optimized DRAMs deliver Top-Notch Performance. Electronic design, Mar 23, 1998, pp. 89-100
157. K.-h. Kim et al., An 8Gb/s/pin 9.6 ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O error-detection Scheme. ISSCC Digest of Technical Papers, Feb 2006, pp.154-155
158. T. Nagai, A 65 nm Low-Power Embedded DRAM with Extended Data-Retention Sleep Mode. ISSCC Digest of Technical Papers, Feb 2006, pp.164-165
159. P. Fazan, Z-RAM zero capacitor Embedded memory technology addresses dual requirements of die size and scalability (Innovative Silicon Inc, 2005). http://clients.concept-web.ch/is/en/technology_white_paper.php#
160. B. Dipert, EEPROM, survival of the fittest, EDN, Jan 15, 1998, pp. 77-90
161. P. Clarke, Intel, Micron offer 128-Gbit NAND flash memory, EETimes, EETIMES, 12-6-2011
162. L. Mearian, Samsung hits high gear, rolls out densest flash chip. Computer world, Apr 11, 2013, http://www.computerworld.com/s/article/9238339/Samsung_hits_high_gear_rolls_out_ densest_flash_chip
163. S. Aritome, NAND Flash Memory Technologies (Wiley, New York, 2015)
164. Y. Cai et al., Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling, in Proceedings of the Conference on Design, Automation and Test, pp. 1285-1290, Mar 2013
165. JEDEC Solid State Technology Association, Stress-Test-Driven Qualification of Integrated Circuits, JESD47G.01, Apr 2010, http://www.jedec.org/
166. Ed Korczynski, 3D-NAND Deposition and Etch Integration. Semiconductor Manufacturing & Design Community, Sept 2016, http://semimd.com/blog/tag/3d-nand/
167. K. Gibb, First Look at Samsung's 48L 3D V-NAND Flash. EE Times, Apr 6, 2016
168. D. Kang et al., 256Gb 3b/Cell V-NAND Flash Memory with 48 Stacked WL Layers. ISSCC Digest of Technical Papers, pp. 130-131
169. K. Gibb, Micron's 3D NAND Innovative Fabrication Process. EE Times, July 13, 2016
170. B. Prince, Vertical 3-D Memory Technologies (Wiley, New York, 2014). ISBN: 978-1-118-76051-2
171. R. Merritt, 3D XPoint Steps Into the Light. EE Times, Jan 14, 2016
172. C. Mellor, Just ONE THOUSAND times BETTER than FLASH! Intel, Micron's amazing claim, 28 Jul 2015, The Register, http://www.theregister.co.uk/2015/07/28/intel_micron_3d_ xpoint/
173. B. Tallis, Samsung at Flash Memory Summit: 64-layer V-NAND, Bigger SSDs, Z-SSD, http://www.anandtech.com/show/10560/, Aug 11, 2016
174. K. Hoya et al., A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode. ISSCC Digest of Technical Papers, Feb 2006, pp. 134-135
175. R. Wilson, MRAM Steps to 16Mbit. Electronics Weekly, June 23, 2004
176. J. Müller et al., Ferroelectric Hafnium Oxide Based Materials and Devices: Assessment of Current Status and Future Prospects. ECS J. Solid State Sci. Technol. 4(5), N30-N35 (2015)
177. J. Müller et al., Ferroelectric Hafnium Oxide: A CMOS-compatible and highly scalable approach to future ferroelectric memories, in International Electronic Device Meeting (IEDM), pp. 280-283 (2013)
178. T.P. Ma, FEDRAM: A capacitor-less DRAM based on ferroelectric-gated field-effect transistor, in 2014 IEEE 6th International Memory Workshop (IMW), 18-21 May 2014
179. Z. Xizhen, FeFET logic circuits for operating a 64 kb FeNAND flash memory array. Integr. Ferroelectr. 132(1), 114-121 (2016)
180. B. Dipert, FRAM: ready to ditch niche? EDN, Apr 10, 1997, pp. 93-107
181. W.Y. Cho et al., A 0.18 m 3.0V 64Mb nonvolatile phase-transition random access memory (PRAM). 2004 ISSCC Digest of Technical Papers (2004), pp. 40-41
182. S. Kang et al., A 0.1 m 1.8V 256Mb 66MHz Synchronous Burst PRAM. ISSCC Digest of Technical Papers, Feb 2006, pp.140-141
183. M. LaPedus, Samsung to ship MCP with phase-change. EE Times 28-04-2010
184. G.W. Burr et al., Phase change memory technology. J. Vac. Sci. Technol. B 28(2), 223-262 (2010)
185. Kurzweil AI, Will phase-change memory replace flash memory? Sept 2013
186. X. Zhou et al., Phase transition characteristics of Al-Sb phase change materials for phase change memory application. Appl. Phys. Lett. 103(7) (2013)
187. X. Chen et al., Buffer-enhanced electrical-pulse-induced-resistive memory effect in thin film perovskites. Jpn. J. Appl. Phys. Part 1 45(3A), 1602-1606 (2006)
188. P. Clarke, Resistive RAM sets chip companies racing. EETimes, 04-24-2006
189. H.Y. Lee et al., Evidence and solution of over-RESET problem for HfOtenrmx based resistive memory with sub-ns switching speed and high endurance, in Proceedings of the IEDM (2010), pp. 19.7.1-19.7.4
190. L. Goux et al., Ultralow sub-500nA operating current high-performance TiNnAl2O3nHfO2nHfnTiN bipolar RRAM achieved through understanding-based stackengineering, in Symposia on VLSI Technology, Digest of Tech. Papers, pp. 159 (2012)
191. T.-Y. Liu, T.H. Yan et al., A 130.7 mm2 two-layer 32-Gbit ReRAM memory device in 24-nm technology. Proc. ISSCC, paper 12.1 (2013)
192. H. Hönigschmid et al., A non-volatile 2 Mbit CBRAM memory core featuring advanced read and program control, in Proceedings of 2006 Symposium on VLSI Circuits, pp. 138-139
193. W.J. Donath, Placement and average interconnections lengths of computer logic. IEEE Trans. Circ. Syst. 26(4), 272 (1979)
194. Semiconductors Industrial Associations, ITRS roadmap, yearly update, http://www.itrs.net
195. SRAM Sessions, International Solid States Circuits Conference 2005 and 2006, ISSCC Digest of Technical Papers, 2005 and 2006
196. A. Fazio et al., ETOXTM Flash Memory Technology: Scaling and Integration Challenges, May 16, 2002, http://developer.intel.com/technology/itj/2002/volume06issue02/art03_ flashmemory/vol6iss2_art03.pdf
197. B. Prince, Semiconductor Memories: A Handbook of Design, Manufacture and Application (Wiley, New York, 1996)
198. W.J. McClean, Status 1999, A report on the IC industry. ICE Corporation, Scottsdale, Arizona (1999)
199. B. Prince, High Performance Memories (Wiley, New York, 1996)
200. IEEE Digest of Technical Papers of the International Solid State Circuit Conference. The ISSCC is held every year in February in San Francisco
201. IEEE Journal of Solid-State Circuits 67. IEDM Digest of Technical Papers, Since 1984
202. A. Abbo et al., XETAL-II: A 107 GOPS, 600mW massively-parallel processor for video scene analysis. ISSCC Digest of Technical Papers, San Francisco, 2007
203. R. Goering, Startup Liga promises to rev simulation, EE Times, 17 July 2006
204. P. Coussy et al., An introduction to high-level synthesis. IEEE Des. Test Comput. 26(4), 8-17 (2009)
205. E. Oruklu et al., System-on-chip design using high-level synthesis tools. Circuits Syst. 3, 1-9 (2012)
206. K. Karras et al., High-level synthesis case study:implementation of a memcached server, in 1st International Workshop on FPGAs for Software Programmers (FSP 2014), Munich, Germany, 1 September 2014
207. S. Sikand, IP Reuse - Design and Verification Report 2013, IC Manage Inc., 2016
208. C. Forzana, D. Pandini, Statistical static timing analysis: a survey. Integr. VLSI J. 42, 409-435 (2009). Elsevier, 2009
209. S.J. Wan et al., Fast and accurate statistical static timing analysis, in IEEE International Symposium on Circuits and Systems (ISCAS), 2014
210. A.M. Baker, Y. Jiang, Modeling and architectural simulations of the statistical static timing analysis of the non-gaussian variation sources for VLSI circuits, in International Journal of Scientific and Research Publications, vol. 3, issue 1 (Trans Tech Publications, Durnten-Zurich, 2013)
211. A. Malik et al., VLSI: techniques for efficient standard cell placement, in IJSE-ITS: Race-2014 (2014). ISSN:2347-2200/V2-N1/PP-17-21
212. A. Hassan, Fundamentals of Floor Planning A Complex SoC. Electronic Design, 21 Mar 2012
213. I. Okhura, et al., A novel basic cell configuration for CMOS gate-array, in Custom Intergrated Circuits Conference 1982, pp 307-310, May 1982
214. H.J.M. Veendrick et al., An efficient and flexible architecture for high-density gate arrays. ISSCC Digest of Technical Papers, San Francisco, 1990
215. Z. Or-Bach, FPGAs as ASIC alternatives: Past and Future. EE Times, 21 Apr 2014
216. See current CPLD architectures on the CPLD vendors websites: Altera, Xilinx, Lattice, Cypres, etc., 2016
217. Structured Arrays/Gate Arrays; FFSA/Fit FAST Structured ARRAY (2014), http://toshiba. semicon-storage.com/eu/product/asic/structured-arrays.html
218. M. Maxfield, Is it an ASIC? Is it an FPGA? No, it's eASIC!. EE Times, 14 Sept 2015
219. H. de Man et al., An intelligent module generator environment, in Proceedings of the 23rd Design Automation Conference, pp. 730-735 (1986)
220. BU-106: Advantages of primary batteries (2016), http://batteryuniversity.com/learn/article/primary_batteries
221. P.G. Bruce et al., Li-O2 and Li-S batteries with high energy storage. Nat. Mater. 11(1), 19-29 (2012). [U. St. Andrews, Scotland]
222. D. Borghino, Lithium-air batteries are getting safer, cheaper, and longer-lasting (2016), http://newatlas.com/lithium-air-batteries/44648/
223. R. Van Noorden, The rechargeable revolution: a better battery. Nature 507, 26-28 (2014)
224. K. Seta et al., 50% Active-Power saving without speed degradation using standby power reduction (SPR) Circuit. IEEE Digest of Technical papers, pp. 318, 319 (1995)
225. T. Kuroda et al., A 0.9V, 150MHz, 10mW, 4mm2, 2D discrete cosine transform core processor with variable threshold voltage (VT) scheme. IEEE J. Solid-State Circuits 1770-1779 (1996)
226. A. Montree et al., Limitations to adaptive back bias approach for standby power reduction in deep sub-micron CMOS ICs, in Proceedings of the '99 European Solid-State Device Research Conference (ESSDERC) 1, 580-583 (1999)
227. T. Chen et al., Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation. IEEE Trans. Very Large Scale Integr. VLSI Syst. 11(5), 888-899 (2003)
228. M. Meijer et al., Limits to performance spread tuning using adaptive voltage and body biasing, in International Symposium on Circuits and Systems (ISCAS), pp. 5-8 (2005)
229. M. Izumikawa et al., A 0.25±m CMOS 0.9V, 100 MHz, DSP core. IEEE J. Solid-State Circuits 32, 52-61 (1997)
230. D. Lee et al., Gate oxide leakage current analysis and reduction for VLSI circuits. IEEE Trans. VLSI Syst. 12(2), 155-166 (2004)
231. International Technology Roadmap for Semiconductors, 2011 Edition; Interconnect, pp. 27-29
232. C. Piguet, Design methods and circuit techniques to reduce leakage in deep submicron, in Faible Tension Faible Consommation, FTFC (2003)
233. H.J.M. Veendrick, Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits. IEEE J. Solid State Circuits SC-19(4), 468-473 (1984)
234. V. Von Kaenel et al., A voltage reduction technique for battery-operated systems. IEEE J. Solid-State Circuits 25, 1136-1140 (1990)
235. J. Pouwelse, Dynamic voltage scaling on a low-power microprocessor, in Proceedings of the 7th Annual International Conference on Mobile Computing and Networking, pp. 251-259 (2001)
236. R. Ghattas et al., Energy management for commodity short-bit-width microcontrollers, in Proceedings of the 2005 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, pp. 32-42 (2005)
237. V. Viswanath, The power of dynamic voltage frequency scaling. EE Times, 20 Aug 2015
238. N. Verma et al., NanometerMOSFET variation in minimum energy subthreshold circuits. IEEE Trans. Electron Devices 55(1), 163-174 (2008)
239. M. Zangeneh et al., Designing tunable subthreshold logic circuits using adaptive feedback equalization. IEEE Trans. Very Large Scale Integr. VLSI Syst. 24(3), 884-889 (2016)
240. K. Yano et al., A 3.8 ns CMOS 16x16-b multiplier using complementary pass-transistor logic. IEEE J. Solid State Circuits 25, 388-393 (1990)
241. M. Suzuki et al., A 1.5 ns 32b CMOS ALU in double pass-transistor logic, in International Solid-State Circuits Conference Digest, pp. 90-91 (1993)
242. A. Parameswar et al., A swing restored pass-transistor logic-based multiply and accumulate circuit for multimedia applications. IEEE J. Solid State Circuits 31, 805-809 (1996)
243. K. Jano et al., Top-down pass-transistor logic design. IEEE J. Solid State Circuits 31, 792-803 (1996)
244. J.H. Pasternak, C. Salama, Differential pass-transistor logic. IEEE Circuits Devices Mag. 9, 23-28 (1993)
245. M. Song et al., Design methodology for high speed and low power digital circuits with energy economized pass-transistor logic (EEPL), in Proceeding of the 22nd ESSCIRC Digest, pp. 120-123 (1996)
246. W.H. Paik et al., Push-pull pass-transistor logic family for low-voltage and low-power, in Proceeding of the 22nd ESSCIRC Digest, pp. 116-119 (1996)
247. R. Zimmermann, W. Fichtner, Low-power logic styles: CMOS versus pass-transistor logic. IEEE J. Solid State Circuits 32, 1079-1090 (1997)
248. Vivekvati et al., A comparative study on reduction in power consumption by switching activity of 8 8 precision multipliers. Int. J. Adamas Tech. Rev. 2(1), 5-10 (2015)
249. C. Mead, L. Conway, in Introduction to VLSI Systems, Chapter 7, ed. by C. Seitz (Addison- Wesley, Reading, MA, 1980)
250. C. Maxfield, To be or not to be asynchronous that is the question. EDN 40, 157-173 (1995)
251. J. Kessels et al., A design experiment for a smart card application consuming low energy, Chapter 13, in Principles of Asynchronous Circuit Design: A Systems Pespective (Kluwer Academic Publishers, Boston, 2001)
252. R A. Lines, Asynchronous interconnect for synchronous (SOC) design. IEEE Micro J. 24(1), 32-41 (2004)
253. A. Bink, ARM996HS, the first licensable, clockless 32-bit processor core. IEEE Micro J. 27, 58-68 (2007)
254. F. te Beest et al., Synchronous full-scan for asynchronous handshake circuits. J. Electron. Test. Theory Appl. 19, 397-406 (2003)
255. R. Hossain et al., Low power design using double edge triggered flip-flops. IEEE Trans. VLSI 2(2), 261-265 (1994)
256. J. Yuang et al., New single-clock CMOS latches and flipflops with improved speed and power savings. IEEE J. Solid State Circuits 32, 62-69 (1997)
257. A.G.M. Strollo et al., Low power double edge-triggered flip-flop using one latch. Electron. Lett. 35, 187-188 (1999)
258. B. Barton et al., ESSCIRC, Low-Power Workshop 1997, Southampton, 1997
259. P.J. Resle et al., A clock distribution network for microprocessors. IEEE J. Solid-State Circuits 36(5), 792-799 (2001)
260. S. Rusu, Clock generation and distribution for high-performance processors, SoC (2004), http://www.tkt.cs.tut.fi/kurssit/8404941/S04/chapter5.pdf
261. S. Henzler, Digital system clocking, from: high-speed digital CMOS circuits, Technical University, Munich, Summer Term 2015
262. K. Bernstein et al., High-Speed CMOS Design Styles (Kluwer Academic Publishers, Boston, 1999)
263. S. Rusu, Circuit design challenges for integrated systems, in Workshop on Integrated Systems, European Solid-State Circuits Conference, September, 1999
264. C. Kim et al., High Bandwidth Memory Interface (Springer Briefs in Electrical and Computer Engineering, New York, 2014)
265. H. Basit et al., Practical Multi-Gigahertz Clocks for ASIC and COT Designs, DesignCon 2004
266. B. Nauta, G. Hoogzaad, How to deal with substrate noise in analog CMOS circuits, in European Conference on Circuit Theory and Design, Budapest, September 1997
267. H.B. Bakoglu, Circuits, Interconnections and Packaging for VLSI (Addison-Wesley, Reading, MA, 1990)
268. E. Dupont et al., Embedded Robustness IPs for transient-error-free ICs. IEEE Des. Test Comput. 19(3), 56-70 (2002)
269. T. Heijmen et al., Soft-error rate testing of deep-submicron integrated circuits, in Test Symposium (ETS '06) (2006)
270. M. Derby, Soft-error impacts on design for reliability technologies. Keynote Talk at IOLTS, July 2007
271. N. Seifert et al., Radiation-induced soft error rates of advanced CMOS bulk devices, in IEEE 44th Annual International Reliability Physics Symposium, San Jose, pp. 217-225 (2006)
272. V. Petrescu et al., A signal integrity self test (SIST) concept for the debug of nanometer CMOS ICs. ISSCC 2006, Digest of Technical Papers, session 29 (2006)
273. P. Drennan et al., Implications of proximity effects for analog design, in IEEE 2006 CICC Conference (2006)
274. J.M. Brunet, Modelling process variability in the design flow. Chip Design Magazine, Issue Dec 2005/Jan 2006
275. M. Vertregt, The analog challenge of nanometer CMOS. IEDM 2006, Digest of Technical Papers, pp. 11-18 (2006)
276. M. Pelgrom et al., Transistor matching in analog CMOS applications, in International Electron Device Meeting (IEDM), pp. 915-918 (1998)
277. V. Moroz, FinFET structure design and variability analysis enabled by TCAD. EE Times, 8 Oct 2012
278. A.R. Brown et al., Impact of metal gate granularity on threshold voltage variability a full-scale three-dimensional statistical simulation study. IEEE Electron Device Lett. 31(11), 1199-1201 (2010)
279. T. Kanamoto et al., Impact of well edge proximity effect on timing. ESSCIRC 2007, Digest of Technical Papers, pp. 115-118 (2007)
280. K. Qian, Variability modeling and statistical parameter extraction for CMOS devices, Dissertation No. UCB/EECS-2015-165, Electrical Engineering and Computer Sciences, University of California at Berkeley, June 2015
281. N. Damrongplasit, Study of variability in advanced transistor technologies, in Electrical Engineering and Computer Sciences, University of California at Berkeley, Fall 2014
282. M. Vertregt, Embedded analog technology. IEDM short course on System-On-a-Chip Technology, 5 Dec 1999
283. P. Stolk et al., Modeling statistical dopant fluctuations in MOS transistors. IEEE Trans. Electron Devices 45(9), 1960-1971 (1998)
284. M. Pelgrom et al., Digital circuit insights from analog experiences, in International Solid-State Circuits Conference 2007, Special Topic Evening Sessions (2007)
285. A. Dadheech et al., Leakage power optimization for 28 nm and beyond. EDN, 07 April 2014
286. A. Agarwal et al., Statistical timing analysis using bounds. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 22(9), 1243-1260 (2003)
287. J.-J. Liou et al, Fast statistical timing analysis by probabilistic event propagation, in DAC 2001, Las Vegas, June 2001
288. A.M. Baker, Y. Jiang, Modeling and architectural simulations of the statistical static timing analysis of the non-gaussian variation sources for VLSI circuits. Int. J. Sci. Res. Publ. 3(1), 1 (2013). ISSN:2250-3153
289. J. Chen, M. Tehranipoor, Critical paths selection and test cost reduction considering process variations, in 2013 22nd Asian Test Symposium, pp. 259-264, 18-21 Nov 2013
290. H.J.M. Veendrick, Wire self-heating in supply lines on bulk-CMOS ICs'. ESSCIRC 2002, Digest of Technical Papers, pp. 199-202, Sept 2002
291. G.D. Wilk et al, High-k dielectrics: current status and materials properties considerations. J. Appl. Phys. 89(10), 5243-5275 (2001)
292. A. Kottantharayil, Low-voltage hot-carrier issues in deep-sub-micron MOSFETs. Thesis, University of Munic, 2001. http://137.193.200.177/ediss/kottantharayil-anil/inhalt.pdf
293. S. Mahaptra et al., Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETs. IEEE Trans. Electron Devices 47(4), 789-796 (2000)
294. S. Tyaginov et al., Understanding and modeling the temperature behavior of hot-carrier degradation in SiON nMOSFETs. IEEE Electron Device Lett. 37(1), 84-87 (2016)
295. K. Kushida-Abdelghafar et al., Effect of nitrogen at SiO2-Si interface on reliability issues negative bias temperature instability and Fowler-Nordheim stress degradation. Appl. Phys. Lett. 81(23), 4362-4364 (2002)
296. Y. Hiruta et al., Interface state generation under long-term positive-bias temperature stress for a p+ poly gate MOS structure. IEEE Trans. Electron Devices 36, 1732 (1989)
297. T.B. Hook et al., The effect of fluorine on parametric and reliability in a 0.18 m 3.5/6.8 nm dual gate oxide CMOS technology. IEEE Trans. Electron Devices 48(7), 1346 (2001)
298. S. Ogawa et al., Interface-trap generartion at ultrathin (4-6 nm) interfaces during negative-bias temperature aging. J. Appl. Phys. 77(3), 1137-1148 (1995)
299. A. Scarpa et al, Effect of the process flow on negative-bias-temperature-instability, in Proceedings of the 8th International Symposium on Process- and Plasma-Induced Damage (2003), p. 142
300. P. Chaparala et al., NBTI in dual gate oxide PMOSFETs, in Proceedings of the 8th International Symposium on Process- and Plasma-Induced Damage (2003), p. 138
301. P. Rani et al., Impact of negative bias temperature instability on 6T CMOS SRAM cell performance. Int. J. Comput. Appl. (0975-8887) 128(12), 1-6 (2015)
302. S. Han et al., In-depth analysis of NBTI at 2X nm node DRAM, in 2016 IEEE 8th International Memory Workshop (IMW) (2016)
303. S. Mahapatra (ed), Fundamentals of Bias Temperature Instability in MOS Transistors. Springer Series in Advanced Microelectronics (Springer, New Delhi, 2016). ISBN 978-81-322-2507-2
304. C.D. Young et al., Investigation of negative bias temperature instability dependence on fin width of silicon-on-insulator-fin-based field effect transistors. J. Appl. Phys. 117, 034501 (2015)
305. B. Linder et al., Process optimizations for NBTI/PBTI for future replacement metal gate technologies, in International Reliability Physics Symposium (2016)
306. R.R. Troutman, Latchup in CMOS Technology (Kluwer Academic Publishers, Boston, 1986). ISBN 0-89838-215-7
307. F. Farbiz, Modeling and suppression of latch-up, Ph. D. dissertation, Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, Illinois, 2010
308. A. Ameraskera, C. Duvvury, ESD in Silicon Integrated Circuits (Wiley, New York, 2002). ISBN 0-471-95481-0
309. M.D. Ker et al, ESD test methods on integrated circuits: an overview, in 8th IEEE International Conference on Electronics, Circuits and Systems 2, 1011-1014 (2001)
310. M. Shen et al., Modeling and design guidelines for P guard rings in lightly doped CMOS substrates. IEEE Trans. Electron Devices 60(9), 2854-2861 (2013)
311. S. Uppal, FinFET reliability, in 2015 IEEE International Integrated Reliability Workshop (IIRW), Oct 2015
312. M.I. Khan, Self-heating and reliability issues in FinFET and 3D ICs, in 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Oct 2014
313. C.A. Chami, Keeping your design files organized, SemiWiki.com, 07 Sept 2016
314. J.-H. Lee et al., ESD in FinFET technologies: past learning and emerging challenges, in IEEE International Reliability Physics Symposium (IRPS) (2013), pp. 2B.5.1-2B.5.8
315. S. Wang et al., A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs, in International Test Conference, pp. 574-583 (2003)
316. L. Peters, DFM: worlds collide, then cooperate, in Semiconductor International, June 2005, www.semiconductor.net
317. P. Rabkin, DFM for advanced technology nodes: fabless view. Future Fab Int. 20 (2006)
318. T. Lizotte, Laser dicing of chip scale and silicon wafer scale packages, in 2003 IEEE/CPMT/SEMl Int'l Electronics Manufacturing Technology Symposium (2003)
319. JEDEC, Joint Electron Devices Engineering Councils, www.jedec.org
320. G.Q. Zhang et al., Mechanics of Microelectronics (Springer, Dordrecht, 2006), www.springer. com
321. J.H.J. Janssen, H.J.M. Veendrick, Spatial and temporal temperature variations in CMOS designs, EDA Publishing/THERMINIC, 2009
322. H. Pape et al., Thermal transient modeling and experimental validation in the European project PROFIT, IEEE Trans. Compon. Packag. Technol. 27(3), 530-538 (2004)
323. K.J. Hess et al., Reliability of bond over active pad structures for 0.13±m CMOS technology, in Proceedings of Electronic Components and Technology Conference, Jan 2003
324. R. Tummala, Moore's law meets its match. IEEE Spectr. 43, 38-43 (2006)
325. K.J. Kuhn, Considerations for ultimate CMOS scaling. IEEE Trans. Electron Devices 59(7), 1813-1828
326. K. de Kort, Techniques for characterization and failure analysis of integrated circuits, in Analysis of Microelectronic Materials and Devices (Wiley, New York, 1991)
327. E.I. Cole, Beam-based defect localization methods, in Microelectronics Failure Analysis Desk Reference Fifth Edition (ASM International, Materials Park, 2005), pp. 406-416
328. F. Beaudoin et al., Principles of thermal laser stimulation techniques, in Microelectronics Failure Analysis Desk Reference, 5th edn. (ASM International, Materials Park, 2005), pp. 417-425
329. R. Giridharagopal, Near-field scanning optical microscopy for through-silicon imaging and fault isolation of integrated circuits, in ISTFA 2014: Proceedings of the 40th International Symposium for Testing and Failure Analysis, Houston, Texas, USA, 9-13 Nov 2014
330. R.A. Falk, Advanced LIVA/TIVA techniques, in Proceedings of the 27th International Symposium for Testing and Failure Analysis, pp. 59-65 (2001)
331. L.A. Giannuzzi, F.A. Stevie (eds.), Introduction to Focused Ion Beams; Instrumentation, Theory, Techniques and Practice (Springer Science + Business Media, Inc., Boston, 2005)
332. H.D. Wanzenboeck, S. Waid, Focused ion beam lithography, in Lithography, vol. 1 (InTech Open Access Publishers/Institute for Solid State Electronics, Vienna University of Technology, Vienna, 2012)
333. FEI, The V400ACE™Focused Ion Beam (FIB) system (2015), www.fei.com/products
334. M. Nourani et al., Detecting signal-overshoots for reliability analysis in high-speed system-onchips. IEEE Trans. Reliab. 51(4), 494-504 (2002)
335. E. Alon et al., Circuits and techniques for high-resolution measurement of on-chip power supply noise. IEEE J. Solid-State Circuits 40(4), 820-828 (2005)
336. D. Schinkel et al., A 1-V 15±W high-precision temperature switch, in Proceedings of the ESSCIRC, pp. 77-80, Sept 2001
337. V. Petrescu et al., A signal-integrity self-test concept for debugging nanometer CMOS ICs. ISSCC Digest of Technical Papers, pp. 544-545, Feb 2006
338. Focused Ion Beam (FIB), Anysilicon (2015). http://anysilicon.com/focused-ion-beam-fib/
339. Semiconductors Industrial Associations, ITRS roadmap, 2013 update, http://www.itrs.net
340. M. Vertregt et al., Scalable high-speed analog circuit design, in 2001 American Academy of Cosmetic Dentistry (Kluwer Academic Publishers, Boston, 2002), pp 3-21
341. M. Izumikawa et al., A 0.25±m 0.9V 100MHz DSP core. IEEE J. Solid-State 32(1), 52-61 (1997)
342. T. Kuroda et al., A 0.9V, 150 MHz, 10mW, 4mm2, 2-D DCT core processor with variable threshold voltage scheme. IEEE J. Solid-State Circuits 1770-1779 (1996)
343. S.H. Lo et al., Quantum-Mechanical modelling of electron tunnelling current from the inversion layer of ultra-thin-oxide in MOSFET's. IEEE Electron Device Lett. 18(5), 209-211 (1997)
344. B. Johnson et al., Market trends: rising costs of production limit availability of leading-edge Fabs', Gartner Report, 17 Sept 2012
345. J. Ribeiro, Samsung investing $14.7 billion in new chip fabrication facility. IDG News Service, 6 Oct 2014
346. H. Jones, Why migration to 20 nm bulk CMOS and 16/14 nm FinFETs is not a best approach for semiconductor industry, White Paper, International Business Strategies, Inc., January 2014
347. C. Piguet, Microelectronics for systems-on-chips, in Coursebooks CSEM, Neuchâtel, Switzerland, 2015/2016
348. F. von Trapp, Executive interview: bill bottoms talks about revamping the ITRS roadmap, 12 Mar 2015, http://www.3dincites.com/2015/03/executive-interview-bill-bottomstalks- revamping-itrs-roadmap/
349. E. Korczynski, 3D-NAND deposition and etch integration, in Semiconductor Manufacturing and Design Community, Sept 2016, http://semimd.com/blog/tag/3d-nand/