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Volumn , Issue , 2016, Pages

In-Depth Analysis of NBTI at 2X nm Node DRAM

Author keywords

Deuterium; DRAM; Interface trap; Negative bias temperature instability; Refresh time; Reliability of MOSFET; SiGe channel

Indexed keywords

DEUTERIUM; MOSFET DEVICES; SILICON; SILICON ALLOYS; STATIC RANDOM ACCESS STORAGE; THERMODYNAMIC STABILITY;

EID: 84984650451     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMW.2016.7495279     Document Type: Conference Paper
Times cited : (3)

References (10)
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  • 2
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  • 3
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  • 4
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    • February-April
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  • 5
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  • 7
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    • BEOL process integrations with Cu/FSG wiring at 90nm design-rule DDR DRAM and their effects on yield, refresh time, and wafer-level reliability
    • N. H. Kwak et al., "BEOL process integrations with Cu/FSG wiring at 90nm design-rule DDR DRAM and their effects on yield, refresh time, and wafer-level reliability," Int. Interconnect Technology Conference, pp. 150-152, 2007.
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  • 8
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  • 10
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.