A reconfigurable dual-port memory with error detection and correction in 28nm FDSOI

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 59, Issue , 2016, Pages 310-312

  Khayatzadeh, Mahmood ^a   Saligane, Mehdi ^a   Wang, Jingcheng ^a   Alioto, Massimo ^b   Blaauw, David ^a   Sylvester, Dennis ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

RANDOM ACCESS STORAGE; RECONFIGURABLE HARDWARE; SYSTEM-ON-CHIP; VOLTAGE SCALING;

BUILDING BLOCKES; DUAL-PORT MEMORY; ERROR DETECTION AND CORRECTION; OPERATING VOLTAGE RANGE; PROCESSOR DESIGN; RECONFIGURABLE; SUPPLY VOLTAGES; SYSTEMS ON CHIPS;

STATIC RANDOM ACCESS STORAGE;

EID: 84962839143     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2016.7418031     Document Type: Conference Paper

References (6)

1. N. Planes et al., "28nm FDSOI technology platform for high-speed low-voltage digital applications, " IEEE Symp. VLSI Circuits, pp. 133-134, Jun. 2012.
2. E. Karl, et al., "A 0. 6V 1. 5GHz 84Mb SRAM Design in 14nm FinFET CMOS Technology, " ISSCC Dig. Tech. Papers, Feb. 2015.
3. J. P. Kulkarni et al, "A 409GOPS/W Adaptive and Resilient Domino Register File in 22nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging, " ISSCC Dig. Tech. Papers, Feb. 2015.
4. E. Karl et al., "A 4. 6GHz 162Mb SRAM design in 22nm trigate CMOS technology with integrated active VMIN enhancing assist circuitry, " ISSCC Dig. Tech. Papers, pp. 230-232, Feb. 2012.
5. F. Frustaci, et al, "A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS, " ISSCC Dig. Tech. Papers, pp. 244-245, Feb. 2014.
6. S. Das et al, "Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance, " IEEE J. Solid-State Circuits, vol. 4, no. 1, pp. 32-48, Jan. 2009.