Top-down pass-transistor logic design

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 6, 1996, Pages 792-803

  Yano, Kazuo ^a,b,c   Sasaki, Yasuhiko ^a,b,d,e   Rikino, Kunihito ^a,f,g   Seki, Koichi ^a,b,d,h,i  

^a HITACHI LTD   (Japan)

^b IEEE

^c WASEDA UNIVERSITY   (Japan)

^d UNIVERSITY OF TOKYO   (Japan)

^e TOHOKU UNIVERSITY

^f TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY   (Japan)

^g Institute of Applied Physics   (Japan)

^h UNIVERSITY OF CALIFORNIA   (United States)

ⁱ JAPAN SOCIETY OF APPLIED PHYSICS   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; LSI CIRCUITS; SEMICONDUCTOR DEVICE STRUCTURES; TRANSISTORS;

CIRCUIT INVENTOR; LEAN INTEGRATION WITH PASS TRANSISTORS; TOP DOWN PASS TRANSISTOR LOGIC; VALUE COST RATIO;

LOGIC CIRCUITS;

EID: 0030166924     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.509865     Document Type: Article

References (22)

1. K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi, and A. Shimizu, "A 3.8 ns CMOS 16 × 16 multiplier using complementary pass-transistor logic," IEEE J. Solid State Circuits, vol. 25, p, 388, 1990.
2. J. H. Pasternak, A. S. Shubat, and C. A. T. Salama, "CMOS differential pass-transistor logic design," IEEE J. Solid State Circuits, vol. 22, p. 216, 1987.
3. M. Suzuki, N. Ohkubo, T. Yamanaka, A. Shimizu, and K. Sasaki, "A 1.5 ns 32 b CMOS ALU in double pass-transistor logic," 1993 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, p. 90, 1993.
4. H. Partovi and D. Draper, "A regenerative push-pull differential logic family," 1994 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, p. 294, 1994.
5. R. H. Krambeck, C. M. Lee, and H-F. S. Law, "High-speed compact circuits with CMOS," IEEE J. Solid State Circuits, vol. SC-17, p. 614, 1982.
6. 2 multiplier array for a 200 MFLOP pipelined coprocessor," 1994 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, p. 290, 1994.
7. A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, "Low-power CMOS digital design," IEEE J. Solid State Circuits, vol. 27, p. 473, 1992.
8. J. H. Pasternak and C. A. T. Salama, "Differential pass-transistor logic," IEEE Circuits and Devices. July, p. 23, 1993.
9. K. Yano, Y. Sasaki, K. Rikino, and K. Seki, "Lean integration: achieving a quantum leap in performance and cost of logic LSI's," in Proc. IEEE 1994 Custom Integrated Circuit Conference, p. 603, 1994.
10. H. Harvey-Horn, "User-defined benchmarks help evaluate 1C physical libraries," Electronics Design, p. 80, Oct. 1993.
11. J. L. Henessy and D. A. Paterson, Computer Architecture: A Quantitative Approach. Los Altos, CA: Morgan Kaufmann, 1990.
12. S. S. Yau and C. K. Tang, "Universal logic modules and their applications," IEEE Trans. Compt., vol. C-19, p. 141, 1970.
13. T. F. Tabloski and F. J. Mowle, "A numerical technique and its application to minimum multiplexer logic circuits," IEEE Trans. Compt., vol. C-25, p. 684, 1976.
14. C. E. Shannon, "The synthesis of two-terminal switching functions," Bell Syst. Tech. J., vol. 28, p. 59, 1949.
15. S. B. Akers, "Binary decision diagram," IEEE Trans. Compt., vol. C-27, p. 509, 1978.
16. R. E. Bryant, "Graph-based algorithm for Boolean function manipulation," IEEE Comput., vol. C-35, p. 677, 1986.
17. S. Minato, N. Ishiura, and S. Yajima, "Shared binary decision diagrams with attribute edges for efficient Boolean function manipulation," Proc. 27th ACM/IEEE Design Automation Conf., p. 52, 1990.
18. R. K. Montoye, P. W. Cook, E. Hokenek, and R. P. Havreiuk, "An 18 ns 56-bit multiply-adder circuit," 1990 IEEE International Solid-State Circuits Conf. Dig. Tech. Papers, p. 46.
19. G. Goto, T. Sato, M. Nakajima, and T. Sukemura, "A 54 X 54-b regularly structured tree multiplier," IEEE J. Solid State Circuits, vol. 27, p. 1229, 1992.
20. R. Murgai, R. Brayton, and A. Sangiovanni-Vincentelli, "An improved synthesis algorithm for multiplexor-based PGA's," 29th ACMI IEEE Design Automation Conf., p. 380, 1992.
21. K. Karplus, "Amap: A technology mapper for selector-based field-programmable gate arrays," in Proc. 28th ACM/IEEE Design Auto-mation Conf., 1991, p. 244.
22. R. J. Landers and S. S. Mahant-Shetti, "Multiplexer-based architecture for high-density, low-power gate arrays," Dig. 1994 Symposium on VLSI Circuits, p. 33, 1994.