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Volumn 24, Issue 3, 2016, Pages 884-896

Designing Tunable Subthreshold Logic Circuits Using Adaptive Feedback Equalization

Author keywords

Feedback equalizer; leakage energy component; subthreshold

Indexed keywords

BUDGET CONTROL; ENERGY UTILIZATION; EQUALIZERS; ERRORS; LOGIC DESIGN; MOSFET DEVICES; TIMING CIRCUITS;

EID: 84928342036     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2015.2421881     Document Type: Article
Times cited : (7)

References (32)
  • 1
    • 11944273157 scopus 로고    scopus 로고
    • A 180-mV subthreshold FFT processor using a minimum energy design methodology
    • Jan.
    • A. Wang and A. Chandrakasan, "A 180-mV subthreshold FFT processor using a minimum energy design methodology," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 310-319, Jan. 2005.
    • (2005) IEEE J. Solid-State Circuits , vol.40 , Issue.1 , pp. 310-319
    • Wang, A.1    Chandrakasan, A.2
  • 2
    • 58149234982 scopus 로고    scopus 로고
    • A 65 nm sub-Vt microcontroller with integrated SRAM and switched capacitor DC-DC converter
    • Jan.
    • J. Kwong, Y. K. Ramadass, N. Verma, and A. P. Chandrakasan, "A 65 nm sub-Vt microcontroller with integrated SRAM and switched capacitor DC-DC converter," IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 115-126, Jan. 2009.
    • (2009) IEEE J. Solid-State Circuits , vol.44 , Issue.1 , pp. 115-126
    • Kwong, J.1    Ramadass, Y.K.2    Verma, N.3    Chandrakasan, A.P.4
  • 4
    • 37749025732 scopus 로고    scopus 로고
    • Nanometer MOSFET variation in minimum energy subthreshold circuits
    • Jan.
    • N. Verma, J. Kwong, and A. P. Chandrakasan, "Nanometer MOSFET variation in minimum energy subthreshold circuits," IEEE Trans. Electron Devices, vol. 55, no. 1, pp. 163-174, Jan. 2008.
    • (2008) IEEE Trans. Electron Devices , vol.55 , Issue.1 , pp. 163-174
    • Verma, N.1    Kwong, J.2    Chandrakasan, A.P.3
  • 6
    • 4444264520 scopus 로고    scopus 로고
    • Novel sizing algorithm for yield improvement under process variation in nanometer technology
    • Jul.
    • S. H. Choi, B. C. Paul, and K. Roy, "Novel sizing algorithm for yield improvement under process variation in nanometer technology," in Proc. 41st Design Autom. Conf., Jul. 2004, pp. 454-459.
    • (2004) Proc. 41st Design Autom. Conf. , pp. 454-459
    • Choi, S.H.1    Paul, B.C.2    Roy, K.3
  • 9
    • 84871841633 scopus 로고    scopus 로고
    • A 62 mV 0.13 μm CMOS standard-cellbased design technique using Schmitt-trigger logic
    • Jan.
    • N. Lotze and Y. Manoli, "A 62 mV 0.13 μm CMOS standard-cellbased design technique using Schmitt-trigger logic," IEEE J. Solid-State Circuits, vol. 47, no. 1, pp. 47-60, Jan. 2012.
    • (2012) IEEE J. Solid-State Circuits , vol.47 , Issue.1 , pp. 47-60
    • Lotze, N.1    Manoli, Y.2
  • 10
    • 77649112185 scopus 로고    scopus 로고
    • An ultra-low-energy multi-standard JPEG co-processor in 65 nm CMOS with sub/near threshold supply voltage
    • Mar.
    • Y. Pu, J. P. de Gyvez, H. Corporaal, and Y. Ha, "An ultra-low-energy multi-standard JPEG co-processor in 65 nm CMOS with sub/near threshold supply voltage," IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 668-680, Mar. 2010.
    • (2010) IEEE J. Solid-State Circuits , vol.45 , Issue.3 , pp. 668-680
    • Pu, Y.1    De Gyvez, J.P.2    Corporaal, H.3    Ha, Y.4
  • 13
    • 27944462775 scopus 로고    scopus 로고
    • A variation-tolerant sub-threshold design approach
    • Jun.
    • N. Jayakumar and S. P. Khatri, "A variation-tolerant sub-threshold design approach," in Proc. 42nd Design Autom. Conf., Jun. 2005, pp. 716-719.
    • (2005) Proc. 42nd Design Autom. Conf. , pp. 716-719
    • Jayakumar, N.1    Khatri, S.P.2
  • 15
    • 34548853428 scopus 로고    scopus 로고
    • A voltage regulator for subthreshold logic with low sensitivity to temperature and process variations
    • Feb.
    • G. De Vita and G. Iannaccone, "A voltage regulator for subthreshold logic with low sensitivity to temperature and process variations," in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers (ISSCC), Feb. 2007, pp. 530-620.
    • (2007) IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers (ISSCC) , pp. 530-620
    • De Vita, G.1    Iannaccone, G.2
  • 16
    • 84866611028 scopus 로고    scopus 로고
    • A 0.25 v 460 nW asynchronous neural signal processor with inherent leakage suppression
    • T.-T. Liu and J. M. Rabaey, "A 0.25 V 460 nW asynchronous neural signal processor with inherent leakage suppression," in Proc. Symp. VLSI Circuits (VLSIC), 2012, pp. 158-159.
    • (2012) Proc. Symp. VLSI Circuits (VLSIC) , pp. 158-159
    • Liu, T.-T.1    Rabaey, J.M.2
  • 17
    • 77952226243 scopus 로고    scopus 로고
    • A 45 nm resilient and adaptive microprocessor core for dynamic variation tolerance
    • Feb.
    • J. Tschanz et al., "A 45 nm resilient and adaptive microprocessor core for dynamic variation tolerance," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers (ISSCC), Feb. 2010, pp. 282-283.
    • (2010) IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers (ISSCC) , pp. 282-283
    • Tschanz, J.1
  • 19
    • 78650879825 scopus 로고    scopus 로고
    • A power-efficient 32 bit ARM processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation
    • Jan.
    • D. Bull, S. Das, K. Shivashankar, G. S. Dasika, K. Flautner, and D. Blaauw, "A power-efficient 32 bit ARM processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation," IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 18-31, Jan. 2011.
    • (2011) IEEE J. Solid-State Circuits , vol.46 , Issue.1 , pp. 18-31
    • Bull, D.1    Das, S.2    Shivashankar, K.3    Dasika, G.S.4    Flautner, K.5    Blaauw, D.6
  • 20
    • 84876579571 scopus 로고    scopus 로고
    • A low-power 1 GHz razor FIR accelerator with time-borrow tracking pipeline and approximate error correction in 65 nm CMOS
    • Feb.
    • P. N. Whatmough, S. Das, and D. M. Bull, "A low-power 1 GHz razor FIR accelerator with time-borrow tracking pipeline and approximate error correction in 65 nm CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers (ISSCC), Feb. 2013, pp. 428-429.
    • (2013) IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers (ISSCC) , pp. 428-429
    • Whatmough, P.N.1    Das, S.2    Bull, D.M.3
  • 22
    • 31344479337 scopus 로고    scopus 로고
    • A 3-Gb/s/ch transceiver for 10-mm uninterrupted RC-limited global on-chip interconnects
    • Jan.
    • D. Schinkel, E. Mensink, E. A. M. Klumperink, E. van Tuijl, and B. Nauta, "A 3-Gb/s/ch transceiver for 10-mm uninterrupted RC-limited global on-chip interconnects," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 297-306, Jan. 2006.
    • (2006) IEEE J. Solid-State Circuits , vol.41 , Issue.1 , pp. 297-306
    • Schinkel, D.1    Mensink, E.2    Klumperink, E.A.M.3    Van Tuijl, E.4    Nauta, B.5
  • 23
    • 84906816046 scopus 로고    scopus 로고
    • Reconfigurable regenerator-based interconnect design for ultra-dynamic-voltage-scaling systems
    • [Online]
    • S. Kim and M. Seok, "Reconfigurable regenerator-based interconnect design for ultra-dynamic-voltage-scaling systems," in Proc. Int. Symp. Low Power Electron. Design (ISLPED), 2014, pp. 99-104. [Online]. Available: http://doi.acm.org/10.1145/2627369.2627632
    • (2014) Proc. Int. Symp. Low Power Electron. Design (ISLPED) , pp. 99-104
    • Kim, S.1    Seok, M.2
  • 25
    • 70349292818 scopus 로고    scopus 로고
    • A 4 Gb/s/ch 356 fJ/b 10 mm equalized on-chip interconnect with nonlinear charge-injecting transmit filter and transimpedance receiver in 90 nm CMOS
    • 67a Feb.
    • B. Kim and V. Stojanović, "A 4 Gb/s/ch 356 fJ/b 10 mm equalized on-chip interconnect with nonlinear charge-injecting transmit filter and transimpedance receiver in 90 nm CMOS," in IEEE Int. Solid-State Circuits Conf.-Dig. Tech. Papers (ISSCC), Feb. 2009, pp. 66-67, 67a.
    • (2009) IEEE Int. Solid-State Circuits Conf.-Dig. Tech. Papers (ISSCC) , pp. 66-67
    • Kim, B.1    Stojanović, V.2
  • 27
    • 84863710609 scopus 로고    scopus 로고
    • Error mitigation in digital logic using a feedback equalization with Schmitt trigger (FEST) circuit
    • Mar.
    • Z. Takhirov, B. Nazer, and A. Joshi, "Error mitigation in digital logic using a feedback equalization with Schmitt trigger (FEST) circuit," in Proc. 13th Int. Symp. Quality Electron. Design (ISQED), Mar. 2012, pp. 312-319.
    • (2012) Proc. 13th Int. Symp. Quality Electron. Design (ISQED) , pp. 312-319
    • Takhirov, Z.1    Nazer, B.2    Joshi, A.3
  • 32
    • 0036105965 scopus 로고    scopus 로고
    • Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage
    • Feb.
    • J. W. Tschanz et al., "Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage," in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers (ISSCC), vol. 1. Feb. 2002, pp. 422-478.
    • (2002) IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers (ISSCC) , vol.1 , pp. 422-478
    • Tschanz, J.W.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.