A 0.25-μm CMOS 0.9-V 100-MHz DSP core

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 1, 1997, Pages 52-60

  Izumikawa, Masanori ^a,b   Igura, Hiroyuki ^a,b   Furuta, Koichiro ^b   Ito, Hiroshi ^b   Wakabayashi, Hitoshi ^b   Nakajima, Ken ^b   Mogami, Tohru ^b   Horiuchi, Tadahiko ^b   Yamashina, Masakazu ^a,b  

^a IEEE   (Japan)

^b NEC CORPORATION   (Japan)

Author keywords

Adders; Digital signal processors; Multiplying circuits; SRAM chips

Indexed keywords

ADDERS; DIGITAL SIGNAL PROCESSING; ELECTRIC INVERTERS; LEAKAGE CURRENTS; MOSFET DEVICES; MULTIPLYING CIRCUITS; NUMERICAL ANALYSIS; RANDOM ACCESS STORAGE; SHORT CIRCUIT CURRENTS; VOLTAGE CONTROL;

DEVICE DEVIATION IMMUNE SENSE AMPLIFIER; SMALL BIT LINE SWING OPERATION; THRESHOLD VOLTAGE;

CMOS INTEGRATED CIRCUITS;

EID: 0030737851     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.553178     Document Type: Article

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