Low-power logic styles: CMOS versus pass-transistor logic

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 7, 1997, Pages 1079-1090

  Zimmermann, Reto ^b,c   Fichtner, Wolfgang ^{a,b,c,d,e,f,g}  

^a IEEE

^b ETH ZURICH   (Switzerland)

^c SWISS FEDERAL INSTITUTE OF TECHNOLOGY   (Switzerland)

^d VIENNA UNIVERSITY OF TECHNOLOGY   (Austria)

^e LUCENT TECHNOLOGIES   (United States)

^f ISE Intgd Systems Engineering AG   (Switzerland)

^g Swiss Natl Academy of Engineering   (Switzerland)

Author keywords

Adder circuits; Complementary CMOS; CPL; Low voltage low power logic styles; Pass transistor logic; VLSI circuit design

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; ELECTRIC NETWORK SYNTHESIS; LOGIC GATES;

COMPLEMENTARY PASS TRANSISTOR LOGICS (CPL); TRANSISTOR SIZING; VOLTAGE SCALING;

TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

EID: 0031189144     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.597298     Document Type: Article

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