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Volumn , Issue , 2012, Pages 197-200

Z2-FET used as 1-transistor high-speed DRAM

Author keywords

[No Author keywords available]

Indexed keywords

ACCESS TIME; CARRIER FLOW; INJECTION BARRIERS; NEW DEVICES; OPERATION MODE; RETENTION TIME; SUBTHRESHOLD SWING; SUPPLY VOLTAGES;

EID: 84870588028     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2012.6343367     Document Type: Conference Paper
Times cited : (22)

References (17)
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  • 4
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    • E. Yoshida and T. Tanaka, "A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory," Electron Devices, IEEE Transactions on, vol. 53, pp. 692-697, 2006.
    • (2006) Electron Devices, IEEE Transactions on , vol.53 , pp. 692-697
    • Yoshida, E.1    Tanaka, T.2
  • 5
    • 67349159445 scopus 로고    scopus 로고
    • Overview and future challenges of floating body ram (fbram) technology for 32 nm technology node and beyond
    • T. Hamamoto and T. Ohsawa, "Overview and future challenges of floating body RAM (FBRAM) technology for 32 nm technology node and beyond," Solid-State Electronics, vol. 53, pp. 676-683, 2009.
    • (2009) Solid-State Electronics , vol.53 , pp. 676-683
    • Hamamoto, T.1    Ohsawa, T.2
  • 7
    • 33847744630 scopus 로고    scopus 로고
    • A novel capacitor-less dram cell using thin capacitively-coupled thyristor (tcct)
    • H. J. Cho, F. Nemati, R. Roy, R. Gupta, K. Yang, et al. , "A novel capacitor-less DRAM cell using thin capacitively-coupled thyristor (TCCT)," in Tech. Dig.-Int. Electron Devices Meet. , 2005, pp. 311-314.
    • (2005) Tech. Dig.-Int. Electron Devices Meet. , pp. 311-314
    • Cho, H.J.1    Nemati, F.2    Roy, R.3    Gupta, R.4    Yang, K.5
  • 9
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    • Optimization of nanoscale thyristors on soi for high-performance high-density memories
    • K. Yang, R. Gupta, S. Banna, F. Nemati, H. J. Cho, M. Ershov, et al. , "Optimization of Nanoscale Thyristors on SOI for High-Performance High-Density Memories," in Intern. SOI Conf. , 2006, pp. 113-114.
    • (2006) Intern. SOI Conf. , pp. 113-114
    • Yang, K.1    Gupta, R.2    Banna, S.3    Nemati, F.4    Cho, H.J.5    Ershov, M.6
  • 13
    • 84856306104 scopus 로고    scopus 로고
    • A compact capacitor-less high-speed dram using field effect-controlled charge regeneration
    • patent no. FR11/03232, Oct. 21 See also the French
    • J. Wan, C. Le Royer, A. Zaslavsky, and S. Cristoloveanu, "A Compact Capacitor-Less High-Speed DRAM Using Field Effect-Controlled Charge Regeneration," Electron Device Letters, IEEE, vol. 33, pp. 179-181, 2012. See also the French patent no. FR11/03232, Oct. 21, 2011.
    • (2011) Electron Device Letters, IEEE , vol.33 , Issue.2012 , pp. 179-181
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  • 15
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    • Tunneling fets on soi: Suppression of ambipolar leakage, low-frequency noise behavior, and modeling
    • J. Wan, C. Le Royer, A. Zaslavsky, and S. Cristoloveanu, "Tunneling FETs on SOI: Suppression of ambipolar leakage, low-frequency noise behavior, and modeling," Solid-State Electronics, vol. 65-66, pp. 226-233, 2011.
    • (2011) Solid-State Electronics , vol.65-66 , pp. 226-233
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  • 16
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.