Critical paths selection and test cost reduction considering process variations

Proceedings of the Asian Test Symposium

Volumn , Issue , 2013, Pages 259-264

  Chen, Jifeng ^a   Tehranipoor, Mohammad ^a  

^a UNIVERSITY OF CONNECTICUT   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COST REDUCTION; SILICON;

CRITICAL PATHS; DELAY DISTRIBUTIONS; PROCESS VARIATION; RING OSCILLATOR; STATIC TIMING ANALYSIS; STATISTICAL STATIC TIMING ANALYSES (SSTA); TEST COST REDUCTION; TIMING ANALYSIS;

TESTING;

EID: 84893502698     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2013.55     Document Type: Conference Paper

References (24)

1. ITRS, "International technology roadmap for semiconductors (itrs) roadmap, " 2011. [Online]. Available: http://www.itrs.net.
2. V. Iyengar, J. Xiong, S. Venkatesan, V. Zolotov, D. Lackey, P. Habitz, and C. Visweswariah, "Statistical test to uncover process variations.".
3. J. Chen and M. Tehranipoor, "A novel flow for reducing clock skew considering nbti effect and process variations, " in Quality Electronic Design (ISQED), 14th International Symposium on, 2013, pp. 327-334.
4. Mango, C.-T. Chao, L.-C. Wang, and K.-T. Cheng, "Pattern selection for testing of deep sub-micron timing defects, " in Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings, vol. 2, Feb., pp. 1060-1065.
5. C.-J. Chang and T. Kobayashi, "Test quality improvement with timingaware atpg: Screening small delay defect case study, " in Test Conference, 2008. ITC 2008. IEEE International, Oct., pp. 1-1.
6. H. Chen, B. Lu, and D.-Z. Du, "Static timing analysis with false paths, " in Computer Design, 2000. Proceedings. 2000 International Conference on, 2000, pp. 541 -544.
7. G. Yu, W. Dong, Z. Feng, and P. Li, "Statistical static timing analysis considering process variation model uncertainty, " Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 27, no. 10, pp. 1880-1890, Oct.
8. M. Sivaraman and A. Strojwas, "Delay fault coverage: A realistic metric and an estimation technique for distributed path delay faults, " in Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on, Nov, pp. 494-501.
9. B. Hargreaves, H. Hult, and S. Reda, "Within-die process variations: How accurately can they be statistically modeled?" in Design Automation Conference, 2008. ASPDAC 2008. Asia and South Pacific, march 2008, pp. 524 -530.
10. S. Padmanaban and S. Tragoudas, "A critical path selection method for delay testing, " in Test Conference, 2004. Proceedings. ITC 2004. International, oct. 2004, pp. 232 - 241.
11. J.-J. Liou, A. Krstic, L.-C. Wang, and K.-T. Cheng, "False-pathaware statistical timing analysis and efficient path selection for delay testing and timing validation, " in Design Automation Conference, 2002. Proceedings. 39th, 2002, pp. 566 - 569.
12. C. Visweswariah, K. Ravindran, K. Kalafala, S. Walker, S. Narayan, D. Beece, J. Piaget, N. Venkateswaran, and J. Hemmett, "First-order incremental block-based statistical timing analysis, " Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 25, no. 10, pp. 2170 -2180, oct. 2006.
13. J. Xiong, V. Zolotov, N. Venkateswaran, and C. Visweswariah, "Criticality computation in parameterized statistical timing, " in Design Automation Conference, 2006 43rd ACM/IEEE, 0-0 2006, pp. 63 -68.
14. V. Iyengar, J. Xiong, S. Venkatesan, V. Zolotov, D. Lackey, P. Habitz, and C. Visweswariah, "Variation-aware performance verification using at-speed structural test and statistical timing, " in Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on, nov. 2007, pp. 405 -412.
15. A. Agarwal, F. Dartu, and D. Blaauw, "Statistical gate delay model considering multiple input switching, " in Proceedings of the 41st annual Design Automation Conference, ser. DAC '04. New York, NY, USA: ACM, 2004, pp. 658-663. [Online]. Available: http://doi.acm.org/10.1145/996566.996746.
16. C. Guardiani, S. Saxena, P. McNamara, P. Schumaker, and D. Coder, "An asymptotically constant, linearly bounded methodology for the statistical simulation of analog circuits including component mismatch effects, " in Design Automation Conference, 2000, pp. 15-18.
17. J. Singh, Z.-Q. Luo, and S. Sapatnekar, "A geometric programmingbased worst case gate sizing method incorporating spatial correlation, " Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 27, no. 2, pp. 295-308, Feruary.
18. T. Sakurai and a. et, "Alpha-power law mosfet model and its application to cmos logic, " in JSSC, 1990, pp. 548-594.
19. Q. Liu and S. S. Sapatnekar, "A framework for scalable postsilicon statistical delay prediction under process variations, " Trans. Comp.- Aided Des. Integ. Cir. Sys., vol. 28, no. 8, pp. 1201-1212, Aug. 2009.
20. [Online]. Available: http://dx.doi.org/10.1109/TCAD.2009.2021732.
21. J. Richard and W. Dean, "Applied multivariate statistical analysis (6th ed), " April 2, 2007.
22. Synopsys. [Online]. Available: http://www.synopsys.com.
23. A. Agarwal, D. Blaauw, V. Zolotov, S. Sundareswaran, M. Zhao, K. Gala, and R. Panda, "Path-based statistical timing analysis considering inter-and intra-die correlations, " in Proc. TAU, 2002, pp. 16-21.
24. M. Bushnell and V. Agrawal, "Essentials of electronic testing (6th ed), " 2000.