Asynchronous interconnect for synchronous SoC design

IEEE Micro

Volumn 24, Issue 1, 2004, Pages 32-41

  Lines, Andrew ^a  

^a Fulcrum Microsystems   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FAILURE ANALYSIS; INTERCONNECTION NETWORKS; PHASE LOCKED LOOPS; SYNCHRONIZATION;

ROUTING CIRCUITS; SYNCHRONOUS CIRCUITS; SYSTEM ON CHIP;

INTEGRATED CIRCUIT LAYOUT;

EID: 1842478716     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2004.1268991     Document Type: Article

References (7)

1. G. Taylor et al., "Point to Point GALS Interconnect," Proc. 8th Int'l Symp. Asynchronous Circuits and Systems (Asych 02), IEEE CS Press, 2002, pp. 69-75.
2. W.J. Bainbridge and S.B. Furber, "Delay-Insensitive System-on-Chip Interconnect Using of 1-of-4 Data Encoding," Proc. 7th Int'l Symp. Asynchronous Circuits and Systems (Asych 01), IEEE CS Press, 2001, pp. 118-126.
3. A.J. Martin, "The Limitations to Delay-Insensitivity in Asynchronous Circuits," Proc. 6th MIT Conf. Advanced Research in VLSI, MIT Press, 1990, pp. 263-278.
4. A. Lines, Pipelined Asynchronous Circuits, master's thesis, CS-TR-95-21, Caltech, 1995.
5. A.J. Martin et al., "The Design of an Asynchronous MIPS R3000 Processor," Proc. 17th Conf. Advanced Research in VLSI, IEEE Press, 1997, pp. 164-161.
6. K. Stevens, "Energy and Performance Models for Clocked and Asynchronous Communication," Proc. 9th Int'l Symp. Asynchronous Circuits and Systems (Asych 03), IEEE CS Press, 2003, pp. 56-66.
7. A. Chakraborty and M. Greenstreet, "Efficient Self-Timed Interfaces for Crossing Clock Domains," Proc. 9th Int'l Symp. Asynchronous Circuits and Systems (Asych 03), IEEE CS Press, 2003, pp. 78-88.