A swing restored pass-transistor logic-based multiply and accumulate circuit for multimedia applications

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 6, 1996, Pages 804-809

  Parameswar, Akilesh ^a,b,c,d,e   Hara, Hiroyuki ^a,c,f,g   Sakurai, Takayasu ^a,c,h,i,j  

^a IEEE

^b Toshiba America Inc   (United States)

^c TOSHIBA CORPORATION   (Japan)

^d UNIVERSITY OF ZIMBABWE   (Zimbabwe)

^e MCMASTER UNIVERSITY   (Canada)

^f SHIBAURA INSTITUTE OF TECHNOLOGY   (Japan)

^g Shibaura Institute of Technology ^*

^h UNIVERSITY OF TOKYO   (Japan)

ⁱ UNIVERSITY OF CALIFORNIA   (United States)

^j JAPAN SOCIETY OF APPLIED PHYSICS   (Japan)

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Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; FLIP FLOP CIRCUITS; GATES (TRANSISTOR); LOGIC DESIGN; MULTIPLYING CIRCUITS; OPTIMIZATION; SIGNAL TO NOISE RATIO; TRANSISTORS; VLSI CIRCUITS;

COMPLIMENTARY PASS TRANSISTOR LOGIC; SWING RESTORED PASS TRANSISTOR LOGIC;

LOGIC CIRCUITS;

EID: 0030166616     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.509866     Document Type: Article

References (7)

1. K. Yano et al., "A 3.8 ns CMOS 16 × 16 multiplier using complimentary pass-transistor logic," IEEE J. Solid-Srate Circuits, vol. 25, no. 2, pp. 388-395, Apr. 1990.
2. M. Suzuki et al., "A 1.5 ns 32-bit CMOS ALU in double pass-transistor logic," in Proc. 1993 IEEE Int. Solid-State Circuits Conf., Feb. 1993, vol. 36, pp. 90-91.
3. F. S. Lai and W. Hwang, "Differential cascode voltage switch with pass gate logic tree for high performance CMOS digital systems," in Proc. 1993 Int. Symp. on VLSI Technology, Systems, and Applications, May 1993, pp. 358-362.
4. L. G. Heller, W. R. Griffin, J. W. Davis, and N. G. Thoma, "Cascode voltage switch logic: A differential CMOS logic family," in Proc. 1984 IEEE Int. Solid-State Circuits Conf., vol. 27, Feb. 1984. pp. 16-17.
5. J. P. Roth, V. G. Oklobdzija, and J. F. Beetem, "Test generation for FET switching circuits," in Proc. 1984 Int. Test Conf., Oct. 1984. pp. 59-62.
6. V. G. Oklobdzija and P. G. Kovijanic, "On testability of CMOS domino logic," in Proc. 14th Int. Conf. on Fault-Tolerant Computing, June 1984, pp. 50-55.
7. M. Matsui et al., "200 MHz video compression macrocells using lowswing differential logic," in Proc. 1994 IEEE Int. Solid-Stale Circuits Conf, Feb. 1994, vol. 37, pp. 76-77.