Implications of pocket optimisation on analog performance in deep sub-micron cmos

European Solid-State Device Research Conference

Volumn 13-15 Sept. 1999, Issue , 1999, Pages 176-179

  Roes, R F M ^a   Van Brandenburg, A C M C ^a   Montree, A H ^a   Woerlee, P H ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS;

ANALOG PERFORMANCE; DEEP SUB-MICRON; DIGITAL CMOS; HALO IMPLANTS; LONG CHANNEL DEVICES; OPTIMISATIONS; SHORT-CHANNEL EFFECT; TRANSISTOR DESIGNS;

DIGITAL DEVICES;

EID: 84907891995     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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3. M. Bohr et al., A high performace 0.25 m logic technology optimized for 1.8 V operation, IEDM 1996, p. 847.
4. T. Hori, A 0.1 m CMOS technology with tilt implated punchthrough stopper (TIPS), IEDM Techn. Digest 1994, p.75.
5. S. Malhi et al, IEEE Circuits and Devices Mag., vol 10(2), pp. 12-17, 1994.
6. Y.V. Ponomaev et al., IEDM Techn. Digest 1997, p. 829.
7. Y.V. Ponomarev et al., IEDM Techn. Digest 1998, p. 635.
8. M. Rodder et al., IEDM'97, p223.