Yield: The key to nanometer profits

EE: Evaluation Engineering

Volumn 44, Issue 3, 2005, Pages 60-66

  Lecklider, Tom ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; COMPUTER SOFTWARE; LITHOGRAPHY; MATHEMATICAL MODELS; NANOTECHNOLOGY; PATTERN RECOGNITION; PROBLEM SOLVING; PROCESS CONTROL; REAL TIME SYSTEMS; SILICON;

CHEMICAL MECHANICAL POLISHING (CMP); DESIGN FOR YIELD (DFY); DESIGN RULE CHECKING (DRC); ELECTRONIC DESIGN AUTOMATION (EDA); EMBEDDED TECHNOLOGY ACCESS (ETA); SYSTEM-ON-A-CHIP (SOC); YIELD ANALYSIS;

PRINTED CIRCUIT DESIGN;

EID: 15744401155     PISSN: 01490370     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Review

References (3)

1. "Accelerating Nanometer Yield Ramp With Yield Diagnostics," Cadence Design Systems, October 2004.
2. Kiugsley, T., "Silicon vs. Layout Verification Pivotal to RET Closure and Yield Ramp-Up," Advanced Reticule Symposium, June 2004.
3. Sawicki, J., "Manufacturing for Design," a presentation made to trade press editors, October 2004, Mentor Graphics.