Highly area efficient and cost effective double stacked S 3(stacked single-crystal Si) peripheral CMOS SSTFT and SRAM cell technology for 512M bit density SRAM

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 265-268

  Jung, Soon Moon ^a   Lim, Hoon ^a   Cho, Wonseok ^a   Cho, Hoosung ^a   Yeo, Chadong ^a   Kang, Yongha ^a   Bae, Daegi ^a   Na, Jonghoon ^a   Kwak, Kunho ^a   Choi, Bonghyun ^a   Kim, Sungjin ^a   Jeong, Jaehun ^a   Chang, Youngchul ^a   Jang, Jaehoon ^a   Kim, Jonghyuk ^a   Kim, Kinam ^a   Ryu, Byung Il ^a  

^a AmorePacific Corporation   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAYS; COST EFFECTIVENESS; LITHOGRAPHY; SILICON; SINGLE CRYSTALS; STATIC RANDOM ACCESS STORAGE; TECHNOLOGY; THRESHOLD VOLTAGE;

CELL EFFICIENCY; CELL SIZE; LAYOUT AREA; LOAD STACKING;

CMOS INTEGRATED CIRCUITS;

EID: 21644471419     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)

1. Soon-Moon Jung et al, VLSI Symp.Tech. Dig., p. 228, 2004.