Low power double edge-triggered flip-flop using one latch

Electronics Letters

Volumn 35, Issue 3, 1999, Pages 187-188

  Strollo, A G M ^a   Napoli, E ^a   Cimino, C ^a  

^a UNIVERSITY OF NAPLES FEDERICO II   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC LOSSES; SEMICONDUCTING SILICON; TIMING CIRCUITS;

DOUBLE EDGE-TRIGGERED (DET) FLIP FLOPS;

FLIP FLOP CIRCUITS;

EID: 0033521780     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19990164     Document Type: Article

References (5)

1. HOSSAIN, R., WRONSKI, L.D., and ALBICKI, A.: 'Low power design using double edge triggered flip-flops', IEEE Trans. VLSI Syst., 1994, 2, (2), pp. 261-265
2. BLAIR, G.M.: 'Low-power double-edge triggered flipflop', Electron. Lett., 1997, 33, (10), pp. 845-847
3. WU, X., and WEI, J.: 'CMOS edge-triggered flip-flop using one latch', Electron. Lett., 1998, 34, (16), pp. 1581-1582
4. PARTOVI, H., BURD, R., SALIM, V., WEBER, F., DIGREGORIO, L., and DRAPER, D.: 'Flow-through latch and edge-triggered flip-flop hybrid elements'. Dig. Tech. Paper ISSCC Conf., 1996, pp. 138-139
5. NAJM, F.N.: 'Transition density: a new measure of activity in digital circuits', IEEE Trans. CAD Integ. Circuits Syst., 1993, 12, (2), pp. 310-323