Hybrid-orientation technology (HOT): Opportunities and challenges

IEEE Transactions on Electron Devices

Volumn 53, Issue 5, 2006, Pages 965-978

  Yang, Min ^a   Chan, Victor W C ^b   Chan, Kevin K ^a   Shi, Leathen ^a   Fried, David M ^b   Stathis, James H ^a   Chou, Anthony I ^b   Gusev, Evgeni ^c   Ott, John A ^a   Burns, Lindsay E ^b   Fischetti, Massimo V ^d   Ieong, Meikei ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b Microelectronics Division   (United States)

^c QUALCOMM INC   (United States)

^d UNIVERSITY OF MASSACHUSETTS   (United States)

Author keywords

Mobility; MOSFET; Silicon; Surface orientation

Indexed keywords

CMOS INTEGRATED CIRCUITS; EPITAXIAL GROWTH; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON WAFERS;

DEVICE STRUCTURES; HYBRID-ORIENTATION TECHNOLOGY (HOT); SILICON SELECTIVE EPITAXY; SURFACE ORIENTATION; WAFER BONDING;

MOSFET DEVICES;

EID: 33646072123     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.872693     Document Type: Review

References (56)

1. J. Kedzierski, E. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, R. Carruthers, C. Cabral, R. Amos, C. Lavoie, R. Roy, J. Newbury, E. Sullivan, J. Benedict, P. Saunders, K. Wong, D. Canaperi, M. Krishnan, K. Lee, B. Rainey, D. Fried, P. Cottrell, H. Wong, M. Ieong, and W. Haensch, "Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation," in IEDM Tech. Dig., 2002, pp. 247-250.
2. E. Nowak, B. Rainey, D. Fried, J. Kedzierski, M. Ieong, W. Leipold, J. Wright, and M. Breitwisch, "A functional FinFET-DGCMOS SRAM cell," in IEDM Tech. Dig., 2002, pp. 411-414.
3. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C. Yang, C. Tabery, C. Ho, Q. Xiang, T. King, J. Bokor, C. Hu, M. Lin, and D. Kyser, "FinFET scaling to 10 nm gate length," in IEDM Tech. Dig., 2002, pp. 251-254.
4. J. Hergenrother, G. Wilk, T. Nigam, et al., "50 nm vertical replacement-gate (VRG) nMOSFET's with ALD HfO2 and A12O3 gate dielectrics," in IEDM Tech. Dig., 2001, pp. 51-54.
5. M. Yang, C.-L. Chang, M. Carroll, and J. C. Sturm, "25 nm p-channel vertical MOSFET's with SiGeC sources/drains," IEEE Electron Device Lett., vol. 20, no. 6, pp. 301-303, Jun. 1999.
6. D. Buchanan, E. Gusev, E. Cartier, et al., "80 nm poly-silicon gated n-FET's with ultrathin A12O3 gate dielectric for ULSI applications," in IEDM Tech. Dig., 2000, p. 223.
7. E. Gusev, D. Buchanan, E. Cartier, et al., "Ultrathin high-k gate stacks for advanced CMOS devices," in IEDM Tech. Dig., 2001, p. 451.
8. B. Doris, Y. Kim, B. Linder, M. Steen, V. Narayanan, D. Boyd, J. Rubino, L. Chang, J. Sleight, A. Topol, E. Sikorski, L. Shi, K. Wong, K. Babich, Y. Zhang, P. Kirsch, J. Newbury, G. Walker, R. Carruthers, C. D'Emic, P. Kozlowski, R. Jammy, K. Guarini, and M. Ieong, "High performance FDSOI CMPS technology with metal gate and high-k," in VLSI Symp. Tech. Dig., 2005, p. 214.
9. C. Hobbs, L. Fonseca, V. Dhandapani, S. Samavedam, B. Taylor, J. Grant, L. Dip, D. Triyoso, R. Hegde, D. Gilmer, R. Garcia, D. Roan, L. Lovejoy, R. Rai, L. Hebert, H. Tseng, B. White, and P. Tobin, "Fermi level pining at the PolySi/Metal oxide interface," in VLSI Symp. Tech. Dig., 2003, pp. 9-10.
10. K. Rim, J. Chu, H. Chen, K. Jenkins, T. Kanarsky, K. Lee, A. Mocuta, H. Zhu, R. Roy, J. Newbury, J. Ott, K. Petrarca, P. Mooney, D. Lacey, S. Koester, K. Chan, D. Boyd, M. Ieong, and H. Wong, "Characteristics and device design of sub-100 nm strained Si N- and pMOSFETs," in VLSI Symp. Tech. Dig., 2002, pp. 98-99.
11. J. Hoyt, H. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E. Fitzgerald, and D. Antoniadis, "Strained silicon MOSFET technology," in IEDM Tech. Dig., 2002, p. 23.
12. C. Ge, C. Lin, C. Ko, C. Huang, Y. Huang, B. Chan, B. Perng, C. Sheu, P. Tsai, L. Yao, C. Wu, T. Lee, C. Chen, C. Wang, S. Lin, Y. Yeo, and C. Hu, "Process-strained Si (PSS) CMOS technology featuring 3D strain engineering," in IEDM Tech. Dig., 2003, pp. 73-76.
13. K. Mistry, M. Armstrong, C. Auth, S. Cea, T. Coan, T. Ghani, T. Hoffmann, A. Murthy, J. Sandford, R. Shaheed, K. Zawadzki, K. Zhang, S. Thompson, and M. Bohr, "Delaying forever: Uniaxial strained silicon transistors in a 90 nm CMOS technology," in VLSI Symp. Tech. Dig., 2004, pp. 50-51.
14. S. Thompson, G. Sun, K. Wu, J. Lim, and T. Nishida, "Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs," in IEDM Tech. Dig., 2004, pp. 221-224.
15. H. Yang, R. Malik, S. Narasimha, Y. Li, R. Divakaruni, P. Agnello, S. Allen, A. Antreasyan, J. Arnold, K. Bandy, M. Belyansky, A. Bonnoit, G. Bronner, V. Chan, X. Chen, Z. Chen, D. Chidambarrao, A. Chou, W. Clark, S. Crowder, B. Engel, H. Harifuchi, S. Huang, R. Jagannathan, F. Jamin, Y. Kohyama, H. Kuroda, C. Lai, H. Lee, W. Lee, E. Lim, W. Lai, A. Mallikarjunan, K. Matsumoto, A. McKnight, J. Nayak, H. Ng, S. Panda, R. Rengarajan, M. Steigerwalk, S. Subbanna, K. Subramanian, J. Sudijono, G. Sudo, S. Sun, B. Tessier, Y. Toyoshima, P. Tran, R. Wise, R. Wong, I. Yang, C. Wann, and L. Su, "Dual stress liner for high performance sub-45 nm gate length SOI CMOS technology," in IEDM Tech. Dig., 2004, pp. 1075-1077.
16. H. Shang, H. Okorn-Schmidt, K. Chan, M. Copel, J. Ott, P. Kozlowski, S. Steen, S. Cordes, H. Wong, E. Jones, and W. Haensch, "High mobility p-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric," in IEDM Tech. Dig., 2002, p. 441.
17. M. Yang, M. Ieong, L. Shi, K. Chan, V. Chan, A. Chou, E. Gusev, K. Jenkins, D. Boyd, Y. Ninomiya, D. Pendleton, Y. Surpris, D. Heenan, J. Ott, K. Guarini, C. D'Emic, M. Cobb, P. Mooney, B. To, N. Rovedo, J. Benedict, R. Mo, and H. Ng, "High performance CMOS fabricated on hybrid substrate with different crystal orientations," in IEDM Tech. Dig., 2003, p. 453.
18. M. Yang, V. Chan, S. H. Ku, M. Ieong, L. Shi, K. K. Chan, C. S. Murthy, R. T. Mo, H. S. Yang, E. A. Lehner, Y. Surpris, F. F. Jamin, P. Oldiges, Y. Zhang, B. N. To, J. R. Holt, S. E. Steen, M. P. Chudzik, D. M. Fried, K. Bernstein, H. Zhu, C. Y. Sung, J. A. Ott, D. C. Boyd, and N. Rovedo, "On the integration of CMOS with hybrid crystal orientations," in VLSI Symp. Tech. Dig., 2004, p. 160.
19. C. D. Sheraw, M. Yang, D. M. Fried, G. Costrini, T. Kanarsky, W.-H. Lee, V. Chan, M. V. Fischetti, J. Holt, L. Black, M. Naeem, S. Panda, L. Economikos, J. Groschopf, A. Kapur, Y. Li, R. T. Mo, A. Bonnoit, D. Degraw, S. Luning, D. Chidambarrao, X. Wang, A. Bryant, D. Brown, P. Agnello, M. Ieong, S.-F. Huang, X. Chen, and M. Khare, "Dual stress liner enhancement in hybrid orientation technology," in VLSI Symp. Tech. Dig., 2005, p. 12.
20. T. Sato, Y. Takeishi, and H. Hara, "Mobility anisotropy of electrons in inversion layers on oxidized silicon surfaces," Phys. Rev. B, Condens. Matter, vol. 4, no. 6, pp. 1950-1960, 1971.
21. G. Cheroff, D. Critchlow, R. Bennard, and L. Terman, "IGFET circuit performance-n-channel versus p-channel," IEEE J. Solid-State Circuits, vol. SSC-4, no. 5, pp. 267-271, Oct. 1969.
22. S. Takagi, A. Toriumi, M. Iwase, and H. Tango, "On the universality of inversion layer mobility in Si MOSFET's part II - Effects of surface orientation," IEEE Trans. Electron Devices, vol. 41, no. 12, pp. 2363-2368, Dec. 1994.
23. B. Goebel, D. Schumann, and E. Bertagnolli, "Vertical n-channel MOSFETs for extremely high density memories: The impact of interface orientation on device performance," IEEE Trans. Electron Devices, vol. 48, no. 5, pp. 897-906, May 2001.
24. H. Sayama, Y. Nishida, H. Oda, T. Oishi, S. Shimizu, T. Kunikiyo, K. Sonoda, Y. Inoue, and M. Inuishi, "Effect of 〈100〉 channel direction for high performance SCE immune pMOSFET with less than 0.15 μm gate length," in IEDM Tech. Dig., 1999, p. 657.
25. T. Matsumoto, S. Maeda, H. Dang, T. Uchida, K. Ota, Y. Hirano, H. Sayama, T. Iwamatsu, T. Ipposhi, H. Oda, S. Maegawa, Y. Inoue, and T. Nishimura, "Novel SOI wafer engineering using low stress and high mobility CMOSFET with 〈100〉-channel for embedded RF/analog applications," in IEDM Tech. Dig., 2002, p. 663.
26. T. Sato, Y. Takeishi, and H. Hara, "Effects of crystallographic orientation on mobility, surface state density, and noise in p-type inversion layers on oxidized silicon surfaces," Jpn. J. Appl. Phys., vol. 8, no. 5, pp. 588-598, May 1969.
27. D. Colman, R. Bate, and J. Mize, "Mobility anisotropy and piezoresistance in silicon p-type inversion layer," J. Appl. Phys., vol. 39, no. 4, pp. 1923-1931, Mar. 1968.
28. M. Fischetti, Z. Ren, P. Solomon, M. Yang, and K. Rim, "Six-band k • p calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness," J. Appl. Phys., vol. 94, no. 2, pp. 1079-1095, Jul. 2003.
29. M. Aoki, K. Yano, T. Masuhara, and K. Shimohigashi, "Fully symmetric cooled CMOS on (110) plane," IEEE Trans. Electron Devices, vol. 36, no. 8, pp. 1429-1433, Aug. 1989.
30. H. Nakamura, T. Ezaki, T. Iwamoto, M. Togo, T. Ikezawa, N. Ikarashi, M. Hane, and T. Yamamoto, "Effects of selecting channel direction in improving performance of sub-100 nm MOSFETs fabricated on (110) surface Si substrate," Jpn. J. Appl. Phys., vol. 43, no. 4B, pp. 1723-1728, 2004.
31. M. Kinugawa, M. Kakumu, T. Usami, and J. Matsunaga, "Effects of silicon surface orientation on submicron CMOS devices," in IEDM Tech. Dig., 1985, p. 581.
32. H. Momose, T. Ohguro, S. Nakamura, Y. Toyoshima, H. Ishiuchi, and H. Iwai, "Ultrathin gate oxide cMOS on (111) surface-oriented Si substrate," IEEE Trans. Electron Devices, vol. 49, no. 9, pp. 1597-1605, Sep. 2002.
33. H. Momose, T. Ohguro, K. Kojima, S. Nakamura, and Y. Toyoshima, "1.5-nm gate oxide CMOS on (110) surface-oriented Si substrate," IEEE Trans. Electron Devices, vol. 50, no. 4, pp. 1001-1008, Apr. 2003.
34. S. Sugawa, I. Ohshima, H. Ishimo, Y. Saito, M. Hirayama, and T. Ohmi, "Advantage of silicon nitride gate insulator transistor by using microwave-excited high-density plasma for applying 100 nm technology node," in IEDM Tech. Dig., 2001, p. 817.
35. A. Teramoto, T. Hamada, H. Akahori, K. Nii, T. Suwa, K. Kotani, M. Hirayama, S. Sugawa, and T. Ohmi, "Low noise balanced-CMOS on Si (110) surface for analog/digital mixed signal circuits," in IEDM Tech. Dig., 2003, p. 801.
36. L. Chang, M. Ieong, and M. Yang, "CMOS circuit performance enhancement by surface orientation optimization," IEEE Trans. Electron Devices, vol. 51, no. 10, pp. 1621-1627, Oct. 2004.
37. M. Yang, E. Gusev, M. Ieong, O. Gluschenkov, D. Boyd, K. Chan, P. Kozlowski, C. D'Emic, R. Sicina, P. Jamison, and A. Chou, "Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO2 gate dielectrics," IEEE Electron Device Lett., vol. 24, no. 5, pp. 339-341, May 2003.
38. M. Kinugawa, M. Kakumu, and J. Matsunaga, "Submicron 3D surface-orientation-optimized CMOS technology," in VLSI Symp. Tech. Dig., 1986, p. 17.
39. B. Doris, Y. Zhang, D. Fried, J. Beinter, O. Dokumaci, W. Natzle, H. Zhu, D. Boyd, J. Holt, J. Petrus, J. Yates, T. Dyer, P. Saunders, M. Steen, E. Nowak, and M. Ieong, "A simplified hybrid orientation technology (SHOT) for high performance CMOS," in VLSI Symp. Tech. Dig., 2004, p. 86.
40. T. Mizuno, N. Sugiyama, T. Tezuka, Y. Moriyama, S. Nakaharai, and S. Takagi, "(110)-surface strained-SOI CMOS devices," IEEE Trans. Electron Devices, vol. 52, no. 3, pp. 367-374, Mar. 2005.
41. Y. Miura, "Effect of orientation on surface charge density at silicon-silicon dioxide interface," Jpn. J. Appl. Phys., vol. 4, no. 12, pp. 958-961, Dec. 1965.
42. VLSI Technology, 2nd ed. S. M. Sze, Ed. New York: McGraw-Hill, 1988, p. 110.
43. Y. Zheng, S. S. Lau, T. Höchbauer, A. Misra, R. Verda, X.-M. He, M. Nastasi, and J. W. Mayer, "Orientation dependence of blistering in H-implanted Si," J. Appl. Phys., vol. 89, no. 5, pp. 2972-2978, Mar. 2001.
44. K. Henttinen, T. Suni, A. Nurmela, I. Suni, V.-M. Airaksinen, and S. S. Lau, Orientation and Boron Concentration Dependence of Silicon Layer Transfer by Mechanical Exfoliation. San Francisco, CA: Mater. Res. Soc., 2001.
45. J. H. Stathis, R. Bolam, M. Yang, T. B. Hook, A. Chou, and G. Larosa, "Interface state generation in pFETs with ultrathin oxide and oxynitride on (100) and (110) Si substrates," Microelectron. Eng., vol. 80, no. 1, pp. 126-129, Jun. 2005.
46. S. Maeda, J. Choi, J. Yang, Y. Jin, S. Bae, Y. Kim, and K. Suh, "Negative bias temperature instability in triple gate transistors," in Proc. Int. Rel. Phys. Symp., 2004, pp. 8-12.
47. S. Zafa, M. Yang, E. Gusev, A. Callegari, J. Stathis, P. Jamison, T. Ning, R. Jammy, and M. Ieong, "A comparative study of NBTI as a function of Si substrate orientation and gate dielectrics (SiON and SiON/ HfO2)," in Proc. VLSI-TSA-TECH, Hsinchu, Taiwan, R.O.C., Apr. 25-27, 2005, pp. 128-129.
48. Q. Xiang, S. Li, D. Wang, K. L. Wang, J. Couillard, and H. Graighead, "Interfacet mass transport and facet evolution in selective epitaxial growth of Si by gas source molecular beam epitaxy," J. Vac. Sci. Technol. B, Microelectron. Process. Phenom., vol. 14, no. 3, pp. 2381-2386, May 1996.
49. Q. Xiang, S. Li, D. Wang, K. Sakamoto, K. L. Wang, G. U'Ren, and M. Goorsky, "Sidewall faceting and inter-facet mass transport in selectively grown epitaxial layers on SiO2-masked Si (110) substrates," J. Cryst. Growth, vol. 175/176, pt. 1, pp. 469-472, May 1997.
50. G. Hobler, H. Vuong, J. Bevk, A. Agarwal, H. Gossmann, and D. Jacobson, "Modeling of ultralow energy boron implantation in silicon," in IEDM Tech. Dig., 1997, p. 489.
51. C. Tian, S. Gara, G. Hobler, and G. Stingeder, "Dependence of boron axial channeling in silicon on crystal orientation," Surf. Interface Anal., vol. 19, no. 1/2, pp. 369-373, 1992.
52. M. S. Lundstrom, "Elementary scattering theory of the Si MOSFET," IEEE Electron Device Lett., vol. 18, no. 7, pp. 361-363, Jul. 1997.
53. M. S. Lundstrom, "On the mobility versus drain-current relation for a nanoscale MOSFET," IEEE Electron Device Lett., vol. 22, no. 6, pp. 293-295, Jun. 2001.
54. G. Shahidi, "SOI technology for the GHz era," IBM J. Res. Develop., vol. 46, no. 2/3, pp. 121-132, 2002.
55. H.-S. P. Wong, D. J. Frank, and P. M. Solomon, "Device design considerations for double-gate, ground-plane, and single-gated ultrathin SOI MOSFET's at the 25 nm channel length generation," in IEDM Tech. Dig., 1998, p. 407.
56. Y. Kanda, "A graphical representation of the piezoresistance coefficients in silicon," IEEE Trans. Electron Devices, vol. ED-29, no. 1, pp. 64-70, Jan. 1982.