High-κ gate dielectrics for nanoscale CMOS devices: Status, challenges, and future

ECS Transactions

Volumn 28, Issue 2, 2010, Pages 39-50

  Park, Dae Gyu ^a   Wang, Xinlin ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; FIELD EFFECT TRANSISTORS; HIGH-K DIELECTRIC; METALS; MOS DEVICES; OXIDE SEMICONDUCTORS; SILICA; SILICON ON INSULATOR TECHNOLOGY; SILICON OXIDES; THRESHOLD VOLTAGE;

COMPLEMENTARY METAL OXIDE SEMICONDUCTORS; HIGH-K/METAL GATES; INDUSTRY STANDARDS; MOBILITY DEGRADATION; NANOSCALE CMOS DEVICES; RANDOM DOPANT FLUCTUATION; RANDOM TELEGRAPH NOISE; SILICON-ON- INSULATORS (SOI);

GATE DIELECTRICS;

EID: 77957736323     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.3372562     Document Type: Conference Paper

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