An 8Gb/s/pin 9.6ns row-cycle 288Mb deca-data rate SDRAM with an I/O error-detection scheme

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2006, Pages

  Kim, Kyu Hyoun ^a   Kang, Uksong ^a   Chung, Hoe Ju ^a   Park, Duk Ha ^a   Kim, Woo Seop ^a   Jang, Young Chan ^a   Park, Moonsook ^a   Lee, Hoon ^a   Kim, Jin Young ^a   Sunwoo, Jung ^a   Park, Hwan Wook ^a   Kim, Hyun Kyung ^a   Chung, Su Jin ^a   Kim, Jae Kwan ^a   Kim, Hyung Seuk ^a   Kwon, Kee Won ^a   Lee, Young Taek ^a   Choi, Joo Sun ^a   Kim, Changhyun ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; ERROR DETECTION; MICROPROCESSOR CHIPS; VOLTAGE MEASUREMENT;

CORE CYCLE SPEED; ERROR-DETECTION SCHEME; SDRAM;

RANDOM ACCESS STORAGE;

EID: 39749169345     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. H. Noda, et al., "A 4.8-ns Random Access 144-Mb Twin-Cell-Memory Fabricated using 0.11-μm Cost-Effective DRAM Technology," Symp. on VLSI Circuits, pp. 188-189, June, 2004.
2. 2 Open-Bit-Line Cell Distributed Over-Driven Sensing and Stacked-Flash Fuse," ISSCC Dig. Tech. Papers, pp. 380-381, Feb., 2001.
3. K-h. Kim, et al., "A 20GB/s 256Mb DRAM with an Inductorless Quadrature PLL and a Cascaded Pre-emphasis Transmitter," ISSCC Dig. Tech. Papers, pp. 470-471, Feb., 2005.
4. K-h. Kim, "Hyper-ring oscillator," US patent, US 2005/0057316 Al, Mar., 2005.
5. F. H. Gebara, J. D. Schaub, A. J. Drake, K. J. Nowka, and R. B. Brown, "4.0GHz 0.18μm CMOS PLL Based on an Interpolate Oscillator," Symp. VLSI Circuits, pp. 100-103, June, 2005.