Cu/Airgap integration on 90nm Cu BEOL process platform

ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Volumn , Issue , 2012, Pages

  Kang, Xiaoxu ^a   Zuo, Qingyun ^a   Wang, Xinxue ^a   Zeng, Shaohai ^a   Chen, Shoumian ^a  

^a Shanghai IC R and D Center   (China)

Author keywords

[No Author keywords available]

Indexed keywords

BASELINE PROCESS; DIELECTRIC FILLING; IMPROVE PERFORMANCE; INTEGRATION SCHEME; METAL INTERCONNECTS; PARASITIC RESISTANCES; PROCESS PLATFORMS; SACRIFICIAL LAYER;

CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; FILLING; MICROELECTRONICS; OPTIMIZATION; PLASMA DENSITY;

INTEGRATION;

EID: 84874843194     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSICT.2012.6467817     Document Type: Conference Paper

References (7)

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