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Volumn , Issue , 2013, Pages

ESD in FinFET technologies: Past learning and emerging challenges

Author keywords

[No Author keywords available]

Indexed keywords

BULK FINFET; ESD PERFORMANCE; ESD PROTECTION DEVICES; GATE DEVICES; HIGH MOBILITY CHANNELS; LARGE CURRENT; NON-SILICON; THERMAL FAILURE;

EID: 84880990313     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2013.6531950     Document Type: Conference Paper
Times cited : (20)

References (18)
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    • Next generation Bulk fin FET devices and their benefits for ESD robustness
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  • 7
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    • Multi-gate devices for the 32 nm technology node and beyond: Challenges for selective epitaxial growth
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  • 8
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    • S. Thijs et al., "Characterization and Optimization of Sub-32 nm Fin FET Devices for ESD Applications,", IEEE Trans. Electron Devices, Vol. 55, no. 12, pp. 3507-3516, 2008.
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    • Thijs, S.1
  • 9
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    • Characterization and modeling of diodes in sub-45 nm CMOS technologies under HBM stress conditions
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  • 10
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  • 11
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  • 13
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  • 14
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  • 16
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.