Exploiting sub-20-nm complementary metal-oxide semiconductor technology challenges to design affordable systems-on-chip

Journal of Micro/ Nanolithography, MEMS, and MOEMS

Volumn 14, Issue 1, 2015, Pages

  Vaidyanathan, Kaushik ^a   Zhu, Qiuling ^a   Liebmann, Lars ^b   Lai, Kafai ^b   Wu, Stephen ^b   Liu, Renzhi ^a   Liu, Yandong ^b   Strojwas, Andzrej ^a   Pileggi, Larry ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b IBM   (United States)

Author keywords

Analog components; Design technology co optimization; Embedded memory; Fin type field effect transistor; Patterning; Standard cell logic; System on chip

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; DIELECTRIC DEVICES; FIELD EFFECT TRANSISTORS; LOGIC SYNTHESIS; METALLIC COMPOUNDS; MICROPROCESSOR CHIPS; MOS DEVICES; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON ON INSULATOR TECHNOLOGY; SYSTEM-ON-CHIP; TRANSISTORS;

ANALOG COMPONENTS; CO-OPTIMIZATION; EMBEDDED MEMORY; FIN TYPES; PATTERNING; STANDARD CELL;

DESIGN;

EID: 84920516997     PISSN: 19325150     EISSN: 19325134     Source Type: Journal    
DOI: 10.1117/1.JMM.14.1.011007     Document Type: Article

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