-
1
-
-
0030408017
-
Statistical metrology: Understanding spatial variation in semiconductor manufacturing
-
Dec.
-
D. Boning and J. Chung, "Statistical metrology: Understanding spatial variation in semiconductor manufacturing," Proc. SPIE, pp. 16-26, Dec. 1996.
-
(1996)
Proc. SPIE
, pp. 16-26
-
-
Boning, D.1
Chung, J.2
-
2
-
-
0003087587
-
Statistical metrology: Measurement and modeling of variation for advanced process development and design rule generation
-
Mar.
-
_, "Statistical metrology: Measurement and modeling of variation for advanced process development and design rule generation," in Proc. Int. Conf. Characterization of Metrology for VLSI Technology, Mar. 1998, pp. 395-404.
-
(1998)
Proc. Int. Conf. Characterization of Metrology for VLSI Technology
, pp. 395-404
-
-
-
3
-
-
0035060746
-
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution
-
Feb.
-
K. A. Bowman, S. G. Duvall, and J. D. Meindl, "Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution," in Proc. 2001 IEEE Solid-State Circuits Conf., Feb. 2001, pp. 278-279.
-
(2001)
Proc. 2001 IEEE Solid-state Circuits Conf.
, pp. 278-279
-
-
Bowman, K.A.1
Duvall, S.G.2
Meindl, J.D.3
-
4
-
-
0032639191
-
Microprocessor reliability performance as a function of die location for a 0.25 μm five layer metal CMOS logic process
-
Mar.
-
W. C. Riodan, R. Miller, J. M. Sherman, and J. Hicks, "Microprocessor reliability performance as a function of die location for a 0.25 μm five layer metal CMOS logic process," in Proc. 1999 IEEE Int. Reliability Physics Symp., Mar. 1999, pp. 1-11.
-
(1999)
Proc. 1999 IEEE Int. Reliability Physics Symp.
, pp. 1-11
-
-
Riodan, W.C.1
Miller, R.2
Sherman, J.M.3
Hicks, J.4
-
5
-
-
0034429814
-
Delay variability: Sources, impacts, and trends
-
Feb.
-
S. Nassif, "Delay variability: Sources, impacts, and trends," in ISSCC Tech. Dig., Feb. 2000, pp. 368-369.
-
(2000)
ISSCC Tech. Dig.
, pp. 368-369
-
-
Nassif, S.1
-
6
-
-
84949959155
-
Timing yield estimation from static timing analysis
-
Mar.
-
A. Gattiker, S. Nassif, R. Dinakar, and C. Long, "Timing yield estimation from static timing analysis," in Proc. 2001 Int. Symp. Quality Electronic Design (ISQED), Mar. 2001, pp. 437-442.
-
(2001)
Proc. 2001 Int. Symp. Quality Electronic Design (ISQED)
, pp. 437-442
-
-
Gattiker, A.1
Nassif, S.2
Dinakar, R.3
Long, C.4
-
7
-
-
0035444711
-
Development of robust interconnect model based on design of experiments and multiobjective optimization
-
Sept.
-
Q. Zhang, J. Liou, J. McMacken, J. Thomson, and P. Payman, "Development of robust interconnect model based on design of experiments and multiobjective optimization," IEEE Trans. Electron Devices, vol. 48, pp. 1885-1891, Sept. 2001.
-
(2001)
IEEE Trans. Electron Devices
, vol.48
, pp. 1885-1891
-
-
Zhang, Q.1
Liou, J.2
McMacken, J.3
Thomson, J.4
Payman, P.5
-
8
-
-
0033711824
-
Wire planning for performance and yield enhancement
-
C. Ouyang, K. Ryu, H. Heineken, J. Khare, S. Shaikh, and M. d'Abreu, "Wire planning for performance and yield enhancement," in Proc. IEEE Custom IC Conf., 2000, pp. 113-116.
-
(2000)
Proc. IEEE Custom IC Conf.
, pp. 113-116
-
-
Ouyang, C.1
Ryu, K.2
Heineken, H.3
Khare, J.4
Shaikh, S.5
D'Abreu, M.6
-
9
-
-
0029484356
-
Channel doping engineering of MOSFET with adaptable threshold voltage using body effect for low voltage and low power applications
-
H. C. Wan et al., "Channel doping engineering of MOSFET with adaptable threshold voltage using body effect for low voltage and low power applications," in Proc. 1995 Int. Symp. VLSI Technology, Systems, and Applications, 1995, pp. 159-163.
-
(1995)
Proc. 1995 Int. Symp. VLSI Technology, Systems, and Applications
, pp. 159-163
-
-
Wan, H.C.1
-
10
-
-
0030086605
-
A 0.9 V 150 MHz 10-mW 2-D discrete cosine trans-form core processor with variable threshold-voltage scheme
-
T. Kuroda et al., "A 0.9 V 150 MHz 10-mW 2-D discrete cosine trans-form core processor with variable threshold-voltage scheme," in ISSCC Tech. Dig., 1996, pp. 166-167.
-
(1996)
ISSCC Tech. Dig.
, pp. 166-167
-
-
Kuroda, T.1
-
11
-
-
0036474788
-
1.2-GIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias
-
Feb.
-
M. Miyazaki, G. Ono, and K. A. Ishibashi, "1.2-GIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias," IEEE J. Solid-State Circuits, vol. 37, pp. 210-217, Feb. 2002.
-
(2002)
IEEE J. Solid-state Circuits
, vol.37
, pp. 210-217
-
-
Miyazaki, M.1
Ono, G.2
Ishibashi, K.A.3
-
12
-
-
0031623211
-
A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSls
-
Aug.
-
M. Miyazaki, H. Mizuno, and K. Ishibashi, "A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSls," in Proc. 1998 Int. Symp. Low-Power Electronics and Design, Aug. 1998, pp. 48-53.
-
(1998)
Proc. 1998 Int. Symp. Low-power Electronics and Design
, pp. 48-53
-
-
Miyazaki, M.1
Mizuno, H.2
Ishibashi, K.3
-
13
-
-
0036105965
-
Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage
-
Feb.
-
J. Tschanz et al., "Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage," in ISSCC Tech. Dig., Feb. 2002, pp. 422-423.
-
(2002)
ISSCC Tech. Dig.
, pp. 422-423
-
-
Tschanz, J.1
-
14
-
-
0000700070
-
Low-power CMOS digital design with dual embedded adaptive power supplies
-
Apr.
-
T. Kuroda and M. Hamada, "Low-power CMOS digital design with dual embedded adaptive power supplies," IEEE J. Solid-State Circuits, vol. 35, pp. 652-655, Apr. 2000.
-
(2000)
IEEE J. Solid-state Circuits
, vol.35
, pp. 652-655
-
-
Kuroda, T.1
Hamada, M.2
-
15
-
-
0035472548
-
On gate level power optimization using dual-supply voltages
-
Oct.
-
C. Chen, A. Srivastava, and M. Sarrafzadeh, "On gate level power optimization using dual-supply voltages," IEEE Trans. VLSI Syst., pp. 616-629, Oct. 2001.
-
(2001)
IEEE Trans. VLSI Syst.
, pp. 616-629
-
-
Chen, C.1
Srivastava, A.2
Sarrafzadeh, M.3
-
16
-
-
0033358770
-
Reducing power consumption of turbo code decoder using adaptive iteration with variable supply voltage
-
Aug.
-
O. Y.-H. Leung, C.-W. Yue, C.-Y. Tsui, and R. S. Cheng, "Reducing power consumption of turbo code decoder using adaptive iteration with variable supply voltage," in Proc. 1999 Int. Symp. Low-Power Electronics and Design, Aug. 1999, pp. 36-41.
-
(1999)
Proc. 1999 Int. Symp. Low-power Electronics and Design
, pp. 36-41
-
-
Leung, O.Y.-H.1
Yue, C.-W.2
Tsui, C.-Y.3
Cheng, R.S.4
-
18
-
-
0033114882
-
A fully digital, energy-efficient, adaptive power-supply regulator
-
Apr.
-
G.-Y. Wei and M. Horowitz, "A fully digital, energy-efficient, adaptive power-supply regulator," IEEE J. Solid-State Circuits, vol. 34, pp. 520-528, Apr. 1999.
-
(1999)
IEEE J. Solid-state Circuits
, vol.34
, pp. 520-528
-
-
Wei, G.-Y.1
Horowitz, M.2
-
19
-
-
0034789923
-
An efficient digital sliding controller for adaptive power supply regulation
-
June
-
J. Kim and R. Horowitz, "An efficient digital sliding controller for adaptive power supply regulation," in Proc. 2001 Symp. VLSI Circuits Dig. Tech. Paper, June 2001, pp. 133-136.
-
(2001)
Proc. 2001 Symp. VLSI Circuits Dig. Tech. Paper
, pp. 133-136
-
-
Kim, J.1
Horowitz, R.2
-
20
-
-
0035421286
-
Low power CMOS design challenges
-
Aug.
-
T. Kuroda, "Low power CMOS design challenges," IEICE Trans. Electron., vol. E84-C, no. 8, pp. 1021-1028, Aug. 2001.
-
(2001)
IEICE Trans. Electron.
, vol.E84-C
, Issue.8
, pp. 1021-1028
-
-
Kuroda, T.1
-
21
-
-
0029419181
-
Statistical threshold-voltage variation and its impact on supply-voltage scaling
-
Oct
-
D. Burnett and S. W. Sun, "Statistical threshold-voltage variation and its impact on supply-voltage scaling," in Proc. Int. Society for Optical Engineering (SPIE), vol. 2636, Oct 1995, pp. 83-90.
-
(1995)
Proc. Int. Society for Optical Engineering (SPIE)
, vol.2636
, pp. 83-90
-
-
Burnett, D.1
Sun, S.W.2
-
22
-
-
0033354320
-
Worst/best device and circuit performances for MOSFET's determined from process fluctuations
-
June
-
O. Prigge, M. Suetake, and M. Miura-Mattausch, "Worst/best device and circuit performances for MOSFET's determined from process fluctuations," IEICE Trans. Electron., vol. E82-C, no. 6, pp. 997-1002, June 1999.
-
(1999)
IEICE Trans. Electron.
, vol.E82-C
, Issue.6
, pp. 997-1002
-
-
Prigge, O.1
Suetake, M.2
Miura-Mattausch, M.3
-
23
-
-
0028430427
-
2 breakdown model for very low voltage lifetime extrapolation
-
May
-
2 breakdown model for very low voltage lifetime extrapolation," IEEE Trans. Electron Devices, vol. 41, pp. 761-767, May 1994.
-
(1994)
IEEE Trans. Electron Devices
, vol.41
, pp. 761-767
-
-
Schuegraf, K.F.1
Hu, C.2
-
24
-
-
0033725602
-
Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling
-
June
-
W. C. Lee and C. Hu, "Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling," in VLSI Technol. Dig., June 2000, pp. 198-199.
-
(2000)
VLSI Technol. Dig.
, pp. 198-199
-
-
Lee, W.C.1
Hu, C.2
-
25
-
-
0021506513
-
A 288 K CMOS pseudostatic RAM
-
Oct
-
H. Kawamoto et al., "A 288 K CMOS pseudostatic RAM," IEEE J. Solid-State Circuits, vol. SC-19, pp. 619-623, Oct 1984.
-
(1984)
IEEE J. Solid-state Circuits
, vol.SC-19
, pp. 619-623
-
-
Kawamoto, H.1
-
26
-
-
0033079570
-
An improved drain-current-conductance method with substrate back-biasing
-
Feb.
-
C. B. Tan et al., "An improved drain-current-conductance method with substrate back-biasing," IEEE trans. Electon Devices, vol. 46, pp. 431-433, Feb. 1999.
-
(1999)
IEEE Trans. Electon Devices
, vol.46
, pp. 431-433
-
-
Tan, C.B.1
-
27
-
-
0034315851
-
A dynamic voltage scaled microprocessor system
-
Nov.
-
T. D. Burd et al., "A dynamic voltage scaled microprocessor system," IEEE J. Solid-State Circuits, vol. 35, pp. 1571-1580, Nov. 2000.
-
(2000)
IEEE J. Solid-state Circuits
, vol.35
, pp. 1571-1580
-
-
Burd, T.D.1
-
28
-
-
0032049972
-
Back-gate bias enhanced band-to-band tunneling leakage in scaled MOSFET's
-
Apr.
-
M.-J. Chen et al., "Back-gate bias enhanced band-to-band tunneling leakage in scaled MOSFET's," IEEE Electron Device Lett., vol. 19, pp. 134-136, Apr. 1998.
-
(1998)
IEEE Electron Device Lett.
, vol.19
, pp. 134-136
-
-
Chen, M.-J.1
-
29
-
-
84907893460
-
Limitations to adaptive back bias approach for standby power reduction in deep sub-micron CMOS
-
Sept.
-
A. H. Montree et al., "Limitations to adaptive back bias approach for standby power reduction in deep sub-micron CMOS," in Proc. '99 European Solid-State Device Research Conf. (ESSDERC), Sept. 1999, pp. 580-583.
-
(1999)
Proc. '99 European Solid-state Device Research Conf. (ESSDERC)
, pp. 580-583
-
-
Montree, A.H.1
|