A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan Designs

IEEE International Test Conference (TC)

Volumn , Issue , 2003, Pages 574-583

  Wang, Seongmoon ^a   Chakradhar, Srimat T ^a  

^a NEC LABORATORIES AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT THEORY; COMPUTER SIMULATION; FLIP FLOP CIRCUITS;

BENCHMARK CIRCUITS;

DIGITAL CIRCUITS;

EID: 0242366119     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

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