New single-clock CMOS latches and flipflops with improved speed and power savings

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 1, 1997, Pages 62-69

  Yuan, Jiren ^a,b,c,d   Svensson, Christer ^a,d,e,f  

^a LINKÖPING UNIVERSITY   (Sweden)

^b Harbin Financial Institute   (China)

^c Research Department   (China)

^d Huang He Machine Factory ^*  (Sweden)

^e CHALMERS UNIVERSITY OF TECHNOLOGY   (Sweden)

^f Roy Swed Acad of Eng Sciences

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED LOGIC DESIGN; ELECTRIC DELAY LINES; INTEGRATED CIRCUIT LAYOUT; LOGIC DEVICES; TIMING CIRCUITS; TRANSISTORS;

DIFFERENTIAL FLIPFLOPS; LOGIC RELATED TRANSISTORS; SINGLE TRANSISTOR CLOCKED DIFFERENTIAL LATCHES; SOFTWARE PACKAGE HSPICE; TRUE SINGLE PHASE CLOCKING (TSPC);

FLIP FLOP CIRCUITS;

EID: 0030828211     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.553179     Document Type: Article

References (12)

1. Y. Ji-ren, I. Karlsson and C. Svensson, "A true sigle-phase-clock dynamic CMOS circuit technique," IEEE J. Solid-State Circuits, vol. SC-22, pp. 899-901, Oct. 1987.
2. J. Yuan and C. Svensson, "High speed CMOS circuit technique," IEEE J. Solid-State Circuits, vol. 24, pp. 62-70, Feb. 1989.
3. C. Svensson and D. Liu, "Low power circuit techniques," in Low Power Design Methodologies, J. M. Rabaey and M. Pedram, Eds. Norwell, MA: Kluwer, 1996, ch. 3.
4. N. Goncalves and H. J. De Man, "NORA: A racefree dynamic CMOS technique for pipelined logic structures," IEEE J. Solid-State Circuits, vol. SC-18, pp. 261-266, 1983.
5. L. G. Heller, W. R. Griffin, J. W. Davis, and N. G. Thoma, "Cascode voltage switch logic: A differential CMOS logic family," in ISSCC Dig. Tech. Papers, 1984, pp. 16-17.
6. D. Renshaw and C. H. Lau, "Race-free clocking of CMOS pipelines using a single global clock," IEEE J Solid-State Circuits, vol. 25, pp. 766-769, June 1990.
7. C. G. Huang, "Implementation of true single-phase clock D flipflops," Electron. Lett., vol. 30, pp. 1373-1374, Aug. 1994.
8. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, 2nd ed. Reading, MA: Addison-Wesley, 1993, ch. 5.
9. Austria Mikro Systeme International, "0.8 μm CMOS process parameters," Dec. 1994.
10. Y. Suzuki, K. Odagawa, and T. Abe, "Clocked CMOS calculator circuitry," IEEE J. Solid-State Circuits, vol. SC-8, pp. 462-469, 1973.
11. J. Yuan, "Efficient CMOS counter circuits," Electron. Lett., vol. 24, pp. 1311-1313, Oct. 1988.
12. H.-T. Huang et al., "Low-voltage low-power CMOS true-single-phase clocking scheme with locally asynchronous logic circuits," in Proc. ISCAS'95, vol. 3, Apr.-May 1995, pp. 1572-1575.