Circuit-level techniques to control gate leakage for sub-100nm CMOS

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 60-63

  Hamzaoglu, Fatih ^a   Stan, Mircea R ^a  

^a UNIVERSITY OF VIRGINIA   (United States)

Author keywords

Domino circuits; Gate leakage; Low power; MTCMOS

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; OXIDES;

CIRCUIT-LEVEL TECHNIQUES; GATE LEAKAGE; VALENCE BAND;

CMOS INTEGRATED CIRCUITS;

EID: 0036948939     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/lpe.2002.146710     Document Type: Conference Paper

References (9)

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