A 65nm low-power embedded DRAM with extended data-retention sleep mode

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2006, Pages

  Nagai, Takeshi ^a   Wada, Masaharu ^a   Iwai, Hitoshi ^a   Kaku, Mariko ^a   Suzuki, Atsushi ^a   Takai, Tomohisa ^a   Itoga, Naoko ^a   Miyazaki, Takayuki ^a   Takenaka, Hiroyuki ^a   Hojo, Takehiko ^a   Miyano, Shinji ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; LEAKAGE CURRENTS; RANDOM ACCESS STORAGE;

DATA-RETENTION POWER; EXTENDED DATA RETENTION (EDR); POWER REDUCTION;

EMBEDDED SYSTEMS;

EID: 39749159371     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)

1. F. Morishita, et al., "A 312MHz 16Mb Random-Cycle Embedded DRAM Macro with 73μW Power-Down Mode for Mobile Applications," ISSCC Dig. Tech. Papers, pp. 202-203, Feb., 2004.